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MSM80C154S MSM83C154S MSM85C154HVS USER'S MANU AL.
Copyright 1988, OKI ELECTRIC INDUSTRY COMPANY, LTD. OKI makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
CONTENTS 1. INTRODUCTION 1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline .................................. 3 1.2 MSM80C154S/MSM83C154S Features ............................................................. 5 1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS .
3. CONTROL 3.1 Oscillators [XTAL1 .2] ....................................................................................... 43 3.2 CPU Resetting .................................................................................................. 45 3.
4.5.2.5.7 Caution about use of timer counters 0 and 1 .................................. 90 4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software power down mode ...................................................................
4.6.4.2 Multi-processor systems ...................................................................... 128 4.7 Interrupt ............................................................................................................. 129 4.7.1 Outline ..
5.7 High Impedance Input Port Setting of Each Quasi-bidirectional Port 1, 2, and 3 ............................................................................................... 207 5.8 100 k W Pull-Up Resistance Setting for Quasi-bidirectional Input Ports 1, 2, and 3 .
1. INTR ODUCTION.
MSM80C154S/83C154S/85C154HVS 2.
INTRODUCTION 3 1. INTRODUCTION 1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline MSM80C154S/MSM83C154S/MSM85C154HVS are single-chip 8-bit fully static microcon- trollers featuring high performance and low power consumption. All MSM80C31F /MSM80C51F instructions and functions have been retained.
MSM80C154S/83C154S/85C154HVS 4 execution from the next address after the stop address where CPU power down mode was activated. Each of the quasi-bidirectional ports 1, 2, and 3 can be set independently as high impedance input ports.
INTRODUCTION 5 1.2 MSM80C154S/MSM83C154S Features • Full static circuitry • Internal program memory (ROM) 16384 words × 8 bits (MSM83C154S) • External program memory (ROM) Connectable up to 64K.
MSM80C154S/83C154S/85C154HVS 6 • Timer/counters (three 16-bit timer/counters) (1) 8-bit timer with 5-bit prescalar (2) 16-bit timer (3) 8-bit timer with 8-bit auto-reloader (4) 8-bit separate timer .
INTRODUCTION 7 1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS In addition to the basic operations of MSM80C31F/MSM80C51F, the MSM80C154S/ MSM83C154S/MSM85C154HVS devices also include the following functions.
MSM80C154S/83C154S/85C154HVS 8.
2. SYSTEM CONFIGURA TION.
MSM80C154S/83C154S/85C154HVS 10.
SYSTEM CONFIGURATION 11 2. SYSTEM CONFIGURATION 2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.
MSM80C154S/83C154S/85C154HVS 12 2.2 MSM80C154S/MSM83C154S pin layouts 1 P1.0/T2 2 P1.1/T2EX 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 P1.7 9 RESET 10 P3.0/RXD 11 P3.1/TXD 12 P3.2/ INT 0 13 P3.3/ INT 1 14 P3.4/T0 15 P3.5/T1/HPDI 16 P3.6/ WR 17 P3.7/ RD 18 XTAL2 19 XTAL1 20 V SS 40 V CC 39 P0.
SYSTEM CONFIGURATION 13 7 P1.5 8 P1.6 9 P1.7 10 RESET 11 P3.0/RXD 12 NC 13 P3.1/TXD 14 P3.2/ INT 0 15 P3.3/ INT 1 16 P3.4/T0 17 P3.5/T1/HPDI MSM80C154SJS/MSM83C154SJS MSM80C154SJS/MSM83C154SJS (Top View) 44 Pin Plastic QFJ P3.6/ WR P3.7/ RD XTAL2 XTAL1 V SS NC P2.
MSM80C154S/83C154S/85C154HVS 14 Applicable Packages 40-Pin Plastic DIP (DIP40-P-600-2.54) 44-Pin Plastic QFJ (QFJ44-P-S650-1.27) 44-Pin Plastic QFP (DFP44-P-910-0.80-2K) 44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K) 40-Pin Ceramic Piggy Back (ADIP40-C-600-2.
SYSTEM CONFIGURATION 15 2.2.1 MSM80C154S/MSM83C154S external dimensions Figure 2-3 MSM80C154S/MSM83C154S external dimensions MSM80C154SRS/MSM83C154SRS 40-pin Plastic DIP (DIP40-P-600-2.54) MSM80C154SJS/MSM83C154SJS 44-Pin Plastic QFJ (QFJ44-P-S650-1.27) MSM80C154SGS/MSM83C154SGS 44-Pin Plastic QFP (QFP44-P-910-0.
MSM80C154S/83C154S/85C154HVS 16 MSM80C154STS/MSM83C154STS 44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K).
SYSTEM CONFIGURATION 17 2.2.2 MSM85C154HVS pin layout and external dimensions * The MSM85C154HVS pin layout of bottom side is the same as the pin layout for MSM83C154SRS.
MSM80C154S/83C154S/85C154HVS 18 2.3 MSM80C154S Block Diagram 256WORD × 8bit TH1 PORT 2 P2.0 P2.7 PORT 0 P0.0 P0.7 PCON IOCON OSC AND TIMING XTAL1 XTAL2 ALE PSEN EA RESET PORT 1 P1.
SYSTEM CONFIGURATION 19 2.4 MSM83C154S Block Diagram TH1 P2.0 P2.7 P0.0 P0.7 XTAL1 XTAL2 ALE PSEN EA RESET P1.0 P1.7 P3.0 P3.7 TL1 TH0 TL0 TMOD TCON IE IP SCON TIMER/COUNTER 0&1 INTERRUPT SERIAL I.
MSM80C154S/83C154S/85C154HVS 20 2.5 MSM85C154HVS Block Diagram TH1 P2.0 P2.7 P0.0 P0.7 XTAL1 XTAL2 ALE PSEN EA RESET P1.0 P1.7 P3.0 P3.7 TL1 TH0 TL0 TMOD TCON IE IP SCON TIMER/COUNTER 0&1 INTERRUP.
SYSTEM CONFIGURATION 21 2.6 Timing and Control 2.6.1 Outline of MSM80C154S/MSM83C154S timing The MSM80C154S/MSM83C154S devices are both equipped with a built-in oscillation inverter (see Figure 2-8) for use in the generation of clock pulses by external crystal or ceramic resonator.
MSM80C154S/83C154S/85C154HVS 22 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 PCL PCL PCL PCL PCL PCL ACC & RAM DPL & Rr PCH PCH PCH PCH DPH & PORT DA.
SYSTEM CONFIGURATION 23 2.6.2 Major synchronizing signals (1) ALE (Address Latch Enable) The ALE signal is used as a clock signal where the address signals 0 thru 7 output from CPU port 0 can be latched externally when external program or external data memory (RAM) is used.
MSM80C154S/83C154S/85C154HVS 24 2.6.3 MSM80C154S fundamental operation time charts S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 or M2 S1 PCL OUT INST IN PCH OUT PCH OUT PCH OUT PCH OUT XTAL1 1 0 ALE 1 0 .
SYSTEM CONFIGURATION 25 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 PCL OUT INST IN PCH OUT PCH OUT PORT 2 LATCH DATA OUT XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT–0 1 0 PORT–2 1 0 PCH OUT Rr OUT ACC DATA .
MSM80C154S/83C154S/85C154HVS 26 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 PCL OUT INST IN PCH OUT PCH OUT DPH OUT XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT–0 1 0 PORT–2 1 0 PCH OUT DPL OUT ACC DATA OUT P.
SYSTEM CONFIGURATION 27 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 PORT 0 LATCH DATA XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT–0 1 0 PORT–2 1 0 Rr OUT EXT RAM DATA FLOATING RD 1 0 PORT 2 LATCH DATA OUT RA.
MSM80C154S/83C154S/85C154HVS 28 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 PORT 0 LATCH DATA XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT–0 1 0 PORT–2 1 0 DPL OUT EXT RAM DATA FLOATING RD 1 0 RAM DATA IN POR.
SYSTEM CONFIGURATION 29 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0,1,2,3 PIN DATA 1 0 CPU DATA SAMPLED 1 0 PIN DATA STABLE Figure 2-20 MSM83C154S MOV direct, PORT[0.
MSM80C154S/83C154S/85C154HVS 30 2.7 Instruction Register (IR) and Instruction Decoder (PLA) MSM80C154S/MSM83C154S operations are based on an instruction code address method.
SYSTEM CONFIGURATION 31 2.8 Arithmetic Operation Section (1) Outline The MSM80C154S/MSM83C154S arithmetic operation section consists of (1) an arithmetic operation instruction decoder, and (2) an arithmetic and logic unit [ALU].
MSM80C154S/83C154S/85C154HVS 32 2.9 Program Counter The MSM80C154S/MSM83C154S program counter has a 16-bit configuration PC 0 thru PC 15 , as shown in Figure 2-23.
SYSTEM CONFIGURATION 33 2.10 Program Memory and External Data Memory 2.10.1 MSM80C154S/MSM83C154S program area and external ROM connections Since MSM80C154S/MSM83C154S are equipped with a 16-bit program counter, these devices can execute programs of up to 64K bytes (including both internal and external programs).
MSM80C154S/83C154S/85C154HVS 34 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MSM74HC373 LATCH P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE P2.0 P2.1 P2.
SYSTEM CONFIGURATION 35 2.10.2 Procedures and circuit connections used when external data memory (RAM) is accessed by data pointer (DPTR) The MSM80C154S/MSM83C154S can be connected to an external 64K word × 8-bit data memory (RAM) when accessing the memory by data pointer (DPTR).
MSM80C154S/83C154S/85C154HVS 36 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MSM74HC373 LATCH P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE P2.0 P2.1 P2.
SYSTEM CONFIGURATION 37 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 PCL PCL PCL PCL PCL PCL ACC DATA DPL INSTRUCTION IN PCH PCH PCH PCH DPH PCH PCH PCH XTAL1 1 .
MSM80C154S/83C154S/85C154HVS 38 2.10.3 Procedures and circuit connections used when external data memory (RAM) is accessed by registers R0 and R1 The MSM80C154S/MSM83C154S can be connected to an external 256 word ¥ 8-bit data memory (RAM) when addressing the memory according to the contents of registers R0 and R1 in the internal data memory (RAM).
SYSTEM CONFIGURATION 39 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MSM74HC373 LATCH P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE RD MSM80C154S/MSM83C154S A0 A1 A2 A3 A4 A5 A6 A7 CS R/ W 7 6 5 4 3 .
MSM80C154S/83C154S/85C154HVS 40 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 PCL PCL PCL PCL PCL PCL ACC DATA Rr INSTRUCTION IN PCH PCH PCH PCH PORT 2 LATCH DATA.
3. CONTR OL.
MSM80C154S/83C154S/85C154HVS 42.
CONTROL 43 3. CONTROL 3.1 Oscillators: XTAL1 XTAL2 An oscillator is formed by connecting a crystal or ceramic resonator between the XTAL1 and XTAL2 pins of the MSM80C154S/MSM83C154S devices. If an external clock is applied to XTAL1, the input should be at 50% duty and C-MOS level.
MSM80C154S/83C154S/85C154HVS 44 IDLE MODE PD & HPD MODE CPU CONTROL CLOCK TIMER, S I/O & INTERRUPT 1M Ω XTAL1 XTAL2 C C * * MSM80C154S/MSM83C154S * The capacity of the compensating capacitor depends on the ceramic resonator. * The XTAL1·2 frequency depends on V CC .
CONTROL 45 3.2 CPU Resetting 3.2.1 Outline If a reset signal (kept at “1” level for at least 1 µ sec) is applied to the RESET pin when the correct voltage (in respect to the various specifications) is applied to the MSM80C154S/ MSM83C154S V CC pin, a reset signal is stored in the CPU even if the XTAL1·2 oscillators have been stopped.
MSM80C154S/83C154S/85C154HVS 46 Figure 3-5 Reset execution time chart (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 PORT DATA XTAL1 1 0 .
CONTROL 47 Figure 3-6 Reset execution time chart (external ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 POR.
MSM80C154S/83C154S/85C154HVS 48 Figure 3-7 Reset release time chart (internal ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT.
CONTROL 49 Figure 3-8 Reset release time chart (external ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 POR.
MSM80C154S/83C154S/85C154HVS 50 3.2.2 Reset Schmitt trigger circuit The Schmitt trigger circuit connected to the RESET pin shown in the MSM80C154S/ MSM- 83C154S reset circuit block diagram in Figure 3-4 operates in the following way when the V CC power supply voltage is +5V.
CONTROL 51 3.2.3 CPU internal status by reset When a reset signal is applied to the CPU with normal voltage applied to the MSM80C154S/ MSM83C154S V CC power supply pin, ports 0, 1, 2, and 3 are set to “1” (input mode) even if XTAL1·2 oscillation has been stopped.
MSM80C154S/83C154S/85C154HVS 52 3.3 EA (CPU Memory Separate) 3.3.1 Outline The function of the EA pin is to determine whether a CPU internal program memory (ROM) instruction or an external program instruction is to be executed.
4. INTERNAL SPECIFICA TIONS.
MSM80C154S/83C154S/85C154HVS 54.
INTERNAL SPECIFICATIONS 55 4. INTERNAL SPECIFICATIONS 4.1 Internal Data Memory (RAM) and Special Function Registers 4.1.1 Outline MSM80C154S/MSM83C154S operation is based on an instruction code addres.
MSM80C154S/83C154S/85C154HVS 56 IOCON B ACC PSW TH2 TL2 RCAP2H RCAP2L T2CON IP P3 IE P2 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0 0FFH~0F8H 0F7H~0F0H 0E7H~0E0H 0D7H~0D0H 0CFH~0C8H 0BFH.
INTERNAL SPECIFICATIONS 57 4.2 Internal Data Memory (RAM) 4.2.1 Internal data memory (RAM) The storage capacity of the MSM80C154S/MSM83C154S data memory is 256 words ¥ 8 bits.
MSM80C154S/83C154S/85C154HVS 58 BANK 3 BANK 2 BANK 1 BANK 0 USER DATA RAM USER DATA RAM 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5.
INTERNAL SPECIFICATIONS 59 4.2.2 Internal data memory registers R0 thru R7 Four banks of registers group exist in the data memory (RAM) between memory addresses 00 thru 1FH. Banks are specified by RS0 and RS1 bit combinations within the program status word (PSW).
MSM80C154S/83C154S/85C154HVS 60 4.2.3 Stack The stack data save (storage) area is in the internal data memory (RAM), and is specified by stack pointer (SP 81H). Although 07H data is automatically set in the stack pointer when the CPU is reset, any desired data can be set by software to enable the data memory to be used as stack from any address.
INTERNAL SPECIFICATIONS 61 4.3 lnternal Data Memory (RAM) Operating Procedures 4.3.1 Internal data memory indirect addressing Operation of the internal data memory indirect increment instruction is described here as an example. This instruction (INC @Rr) is a 1-byte 1-machine cycle instruction (see Figure 4- 4).
MSM80C154S/83C154S/85C154HVS 62 4.3.2 Internal data memory register R0 thru R7 designation Operation of the internal data memory register decrement instruction is described here as an example. This instruction (DEC Rr) is a 1-byte 1-machine cycle instruction (see Figure 4-5).
INTERNAL SPECIFICATIONS 63 4.3.3 Internal data memory 1-bit data designation In the MSM80C154S/MSM83C154S, 1-bit data manipulations (test, reset, set, complement, transfer) can be executed directly between internal data memory addresses 20 thru 2FH by bit manipulation instructions.
MSM80C154S/83C154S/85C154HVS 64 Table 4-4 Bit designation table Bit name Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 b 2 b 1 b 0 000 001 010 011 100 101 110 111 Table 4-5 Addressing combination ta.
INTERNAL SPECIFICATIONS 65 4.4 Special Function Registers (TCON, SCON,.... ACC, B) 4.4.1 Outline As can be seen from the configuration shown in Table 4-6, the MSM80C154S/ MSM83C154S special function registers consist of 27 8-bit registers. Special function registers can be accessed (R/W) by either data addressing or bit addressing.
MSM80C154S/83C154S/85C154HVS 66 Table 4-6 List of special function registers b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 D6 D5 D4 D3 D2 D.
INTERNAL SPECIFICATIONS 67 4.4.2 Special function registers 4.4.2.1 Timer mode register (TMOD) TMOD 89H GATE C/ T M1 M0 GATE C/ T M1 M0 Name Address MSB LSB 76543210 Bit location Flag Function TMOD.
MSM80C154S/83C154S/85C154HVS 68 4.4.2.2 Power control register (PCON) PCON 87H SMOD HPD RPD — GF1 GF0 PD IDL Name Address MSB LSB 76543210 Bit location Flag Function PCON.0 PCON.1 PCON.2 PCON.3 PCON.4 PCON.5 PCON.6 PCON.7 IDL PD GF0 GF1 — RPD HPD SMOD IDLE mode set when this bit is set to "1".
INTERNAL SPECIFICATIONS 69 4.4.2.3 Timer control register (TCON) TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Name Address MSB LSB 76543210 Bit location Flag Function TCON.
MSM80C154S/83C154S/85C154HVS 70 4.4.2.4 Serial port control register (SCON) SCON 98H SM0 SM1 SM2 REN TB8 RB8 TI RI Name Address MSB LSB 76543210 Bit location Flag Function SCON.0 SCON.1 SCON.2 SCON.3 SCON.4 SCON.5 SCON.6 SCON.7 RI TI RB8 TB8 REN SM2 SM1 SM0 "End of serial port reception" interrupt request flag.
INTERNAL SPECIFICATIONS 71 4.4.2.5 Interrupt enable register (IE) IE 0A8H EA — ET2 ES ET1 EX1 ET0 EX0 Name Address MSB LSB 76543210 Bit location Flag Function IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 IE.6 IE.7 EX0 ET0 EX1 ET1 ES ET2 — EA Interrupt control bit for external interrupt 0.
MSM80C154S/83C154S/85C154HVS 72 4.4.2.6 Interrupt priority register (IP) IP 0B8H PCT — PT2 PS PT1 PX1 PT0 PX0 Name Address MSB LSB 76543210 Bit location Flag Function IP.0 IP.1 IP.2 IP.3 IP.4 IP.5 IP.6 IP.7 PX0 PT0 PX1 PT1 PS PT2 — PCT Interrupt priority bit for external interrupt 0.
INTERNAL SPECIFICATIONS 73 4.4.2.7 Program status word register (PSW) PSW 0D0H CY AC F0 RS1 RS0 OV F1 P Name Address MSB LSB 76543210 Bit location Flag Function PSW.0 PSW.1 PSW.2 PSW.3 PSW.4 PSW.5 PSW.6 PSW.7 P F1 OV RS0 RS1 F0 AC CY Accumulator (ACC) parity indicator.
MSM80C154S/83C154S/85C154HVS 74 4.4.2.8 I/O control register (IOCON) IOCON 0F8H — T32 SERR IZC P3HZ P2HZ P1HZ ALF Name Address MSB LSB 76543210 Bit location Flag Function IOCON.
INTERNAL SPECIFICATIONS 75 4.4.2.9 Timer 2 control register (T2CON) TMOD 0C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ T2 CP/ RL2 Name Address MSB LSB 76543210 Bit location Flag Function T2CON.
MSM80C154S/83C154S/85C154HVS 76 4.5 Timer/Counters 0, 1 and 2 4.5.1 Outline Timer/counters 0, 1 and 2 are all equipped with 16-bit binary up-counting and Read/Write functions, and can be operated independently. All control of timer/counters 0 and 1 is handled by the timer control register (TCON 88H) and the timer mode register (TMOD 89H).
INTERNAL SPECIFICATIONS 77 Figure 4-7 Overall clock input control circuit for timer/counters 0 and 1 TIMER 1 GATE C/ T M1 M0 GATE C/ T M1 M0 76543210 TIMER MODE REGISTER (TMOD) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 76543210 TIMER CONTROL REGISTER (TCON) TIMER 0 DETECTOR T1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 78 4.5.2.3 Timer/counter 0 and 1 count clock designation Designation of count clock inputs to timer/counters 0 and 1 is controlled by bit 2 and 6, C/ T , in the timer mode register (TMOD 89H). Timer/counter 0 is controlled by bit 2, C/ T , and timer/counter 1 is controlled by bit 6, C/ T .
INTERNAL SPECIFICATIONS 79 4.5.2.3.1 External clock detector circuit for timer/counters 0 and 1 The detector circuit shown in Figure 4-8 is inserted between the timer/counters and the external clock pin. This detector circuit operates in the following way.
MSM80C154S/83C154S/85C154HVS 80 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 or M2 S1 XTAL1 1 0 ALE 1 0 T0 or T1 COUNT IN 1 0 F/F2Q 1 0 TIMER COUNT 1 0 F/F1Q 1 0 S2 S6 Figure 4-9 Detector circuit operational time chart 4.
INTERNAL SPECIFICATIONS 81 TIMER 0 or TIMER 1 CLOCK DETECTOR XTAL 1 ÷ 12 S3 Q D L S5 INT0 or INT1 ✽ GATE TR0 or TR1 T0 or T1 C/ T Figure 4-10 INT 0 and INT 1 timer/counter start/stop control circui.
MSM80C154S/83C154S/85C154HVS 82 4.5.2.5 Timer/counters 0/1 timer modes 4.5.2.5.1 Outline The timer/counter 0 and 1 timer modes are set by combinations of M0 and M1 bit data in the timer mode register (TMOD 89H) shown in Table 4-11. The timer modes which can be set are 0, 1, 2, and 3.
INTERNAL SPECIFICATIONS 83 DETECTOR XTAL 1 ÷ 12 S3 GATE C/ T DATA INT 0 PIN (PORT 3.2) LATCH S5 Q TR0 T0 PIN (PORT 3.4) Q0------Q4 TL0 (5BITS) Q0------Q7 TH0 (8BITS) C DETECTOR TF0 Figure 4-11 Timer/counter 0 mode 0 DETECTOR XTAL 1 ÷ 12 S3 GATE C/ T DATA INT 1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 84 4.5.2.5.3 Mode 1 M1 M0 01 In mode 1, timer/counters 0 and 1 both become 16-bit timer/counters by the circuit connection shown in Figures 4-13 and 4-14. TL0 and TL1 in timer/counters 0 and 1 serve as the counter for the eight lower bits, and TH0 and TH1 serve as the counter for the eight upper bits.
INTERNAL SPECIFICATIONS 85 DETECTOR XTAL 1 ÷ 12 S3 GATE C/ T DATA INT 0 PIN (PORT 3.2) LATCH S5 Q TR0 T0 PIN (PORT 3.4) Q0------Q7 TL0 (8BITS) Q0------Q7 TH0 (8BITS) C DETECTOR TF0 Figure 4-13 Timer/counter 0 model DETECTOR XTAL 1 ÷ 12 S3 GATE C/ T DATA INT 1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 86 4.5.2.5.4 Mode 2 M1 M0 10 In mode 2, timer/counters 0 and 1 both become 8-bit timer/counters with 8-bit auto reloader registers by the circuit connection shown in Figures 4-15 and 4-16.
INTERNAL SPECIFICATIONS 87 DETECTOR XTAL 1 ÷ 12 S3 GATE C/ T DATA INT 0 PIN (PORT 3.2) LATCH S5 Q TR0 T0 PIN (PORT 3.4) Q0------Q7 TL0 (8BITS) C DETECTOR TF0 Q0------Q7 TH0 (8BITS) RELOAD DATA Figure 4-15 Timer/counter 0 mode 2 DETECTOR XTAL 1 ÷ 12 S3 GATE C/ T DATA INT 1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 88 4.5.2.5.5 Mode 3 M1 M0 11 In mode 3, timer/counter 0 TL0 and TH0 become independent 8-bit timer/counters by the circuit connection shown in Figure 4-17.
INTERNAL SPECIFICATIONS 89 4.5.2.5.6 32-bit timer mode When “1” is set in bit 6 (T32) of the I/O control register (IOCON 0F8H), timer/counters 0 and 1 are connected serially as indicated in Figure 4-18 to become a 32-bit timer/counter. This 32-bit timer/counter is started by the following procedure.
MSM80C154S/83C154S/85C154HVS 90 4.5.2.5.7 Caution about use of timer counters 0 and 1 Since the internal clock stops operation during soft power down mode (PD), the auto-reload operation is not executed if timer/counters 0 and 1 are set to mode 2 or mode 3.
INTERNAL SPECIFICATIONS 91 4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software power down mode When setting sofware power down mode, if the value of a timer counter by which a timer interrupt is set is immediately before overflow, the software power down mode can not be set.
MSM80C154S/83C154S/85C154HVS 92 4.5.3 Timer/counter 2 4.5.3.1 Outline Timer/counter 2 is equipped with 16-bit binary counting and Read/Write functions. This timer/ counter is controlled entirely by timer 2 control register (T2CON 0C8H). The operating modes are 16-bit auto reload mode, capture mode, and baud rate generator mode.
INTERNAL SPECIFICATIONS 93 EXF2 : Timer/counter 2 external flag bit which is set when the T2EX pin level (bit 1 of port 1) is changed from “1” to “0” at EXEN2=1. This flag serves as the timer interrupt 2 request signal. When an interrupt is generated, this flag must be reset to “0” by software.
MSM80C154S/83C154S/85C154HVS 94 XTAL 1 ÷ 12 S3 DETECTOR T2 [PORT 1.0] Q0------Q7 TL2 8 BIT C RCAP2L Q0------Q7 TH2 8 BIT C RCAP2H DETECTOR T2EX [PORT 1.1] TR2 EXEN2 DETECTOR DETECTOR TF2 EXF2 TIMER 2 INTERRUPT RCLK=0 TCLK=0 CP/ RL2 =0 C/ T2 Figure 4-20 Timer/counter 2 16-bit auto reload mode circuit 4.
INTERNAL SPECIFICATIONS 95 XTAL 1 ÷ 12 S3 DETECTOR T2 [PORT 1.0] Q0------Q7 TL2 8 BIT C RCAP2L Q0------Q7 TH2 8 BIT C RCAP2H DETECTOR T2EX [PORT 1.1] TR2 EXEN2 DETECTOR DETECTOR TF2 EXF2 TIMER 2 INTERRUPT RCLK=0 TCLK=0 CP/ RL2 =1 C/ T2 Figure 4-21 Timer/counter 2 16-bit capture mode circuit 4.
MSM80C154S/83C154S/85C154HVS 96 XTAL 1 ÷ 2 S3 DETECTOR T2 [PORT 1.0] Q0------Q7 TL2 8 BIT C RCAP2L Q0------Q7 TH2 8 BIT C RCAP2H DETECTOR T2EX [PORT 1.
INTERNAL SPECIFICATIONS 97 4.5.3.4 Timer/counter 2 detector circuit 4.5.3.4.1 T2 (timer/counter 2 external clock detector) The T2 detector circuit block diagram is shown in Figure 4-23.
MSM80C154S/83C154S/85C154HVS 98 4.5.3.5 Timer/counter carry signal detector circuit The detector circuit shown in Figure 4-25 is inserted between the MSM80C154S/ MSM83C154S timer/counter carry output and the timer flag.
INTERNAL SPECIFICATIONS 99 4.6 Serial Port 4.6.1 Outline MSM80C154S/MSM83C154S is equipped with a serial port which can be used in I/O extension and UART (Universal Asynchronous Receiver/Transmitter) applications. I/O extension mode • Input and output of 8-bit serial data synchronized with the MSM80C154S/MSM83C154S output clock.
MSM80C154S/83C154S/85C154HVS 100 SCON SMOD TCLK RCLK SERR TX CONTROL RX CONTROL (PCON.7) (T2CON.4) (T2CON.5) (IOCON.5) SBUF (R) INPUT SHIFT REGISTER SBUF (T) MULTIPLEXER RXD (P3.0) MULTIPLEXER TXD (P3.1) SHIFT CLOCK INTERNAL BUS TIMER/COUNTER1 OVERFLOW TIMER/COUNTER2 OVERFLOW 1/2OSC.
INTERNAL SPECIFICATIONS 101 4.6.2 Special function registers for serial port 4.6.2.1 SCON (Serial Port Control Register) SCON is an 8-bit special function register consisting of control bits for speci.
MSM80C154S/83C154S/85C154HVS 102 Table 4-15 SCON Bit Symbol Function 0 1 2 3 4 5 6 7 RI TI RB8 TB8 REN SM2 SM1 SM0 "End of reception" flag. This is the interrupt request flag set by hardware when reception of one frame has been completed. The interrupt is generated by ORing with the T1 flag.
INTERNAL SPECIFICATIONS 103 Table 4-16 Serial port operation modes SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Function I/O extension 10-bit frame UART 11-bit frame UART 11-bit frame UART Baud rate 1/12 F OSC Vareable 1/32 F OSC or 1/64 F OSC Vareable Note: F OSC denotes frequency of fundamental oscillator (XTAL1·2).
MSM80C154S/83C154S/85C154HVS 104 4.6.2.5 SMOD SMOD controls the division of the baud rate clock source when the serial port is in UART mode (mode 1, 2, or 3). If SMOD is cleared when in mode 1 or 3, the timer/counter 1 overflow frequency divided by 2 becomes the baud rate clock source.
INTERNAL SPECIFICATIONS 105 4.6.2.6 SERR SERR is the status flag set when a framing error or overrun error is generated during UART mode (mode 1, 2, or 3). Framing error: The SERR flag is set when no stop bit is detected in UART mode. Framing error is detected irrespective of the data reception conditions set by SM2.
MSM80C154S/83C154S/85C154HVS 106 4.6.3 Operating modes 4.6.3.1 Mode 0 4.6.3.1.1 Outline Mode 0 is the I/O extension mode where input and output of 8-bit data via RXD (P3.
INTERNAL SPECIFICATIONS 107 SBUF (R) INPUT SHIFT REG. INTERNAL BUS RI SBUF (T) START START INTERNAL BUS TI REN SHIFT CLOCK ENABLE TXD RXD WRITE TO SBUF SERIAL PORT INTERRUPT Figure 4-28 Serial port (m.
MSM80C154S/83C154S/85C154HVS 108 Figure 4-29 Serial port (mode 0) timing chart D1 WRITE TO SBUF RXD TXD ALE S4 S5 S6 S1 S2 S3 TERMINATE TRANSMISSION TI S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 .
INTERNAL SPECIFICATIONS 109 Figure 4-30 Serial port (mode 0) timing and corresponding basic MSM80C154S/ MSM83C154S timing XTAL1 ALE OUTPUT: READ RXD INPUT: TXD (SHIFT CLOCK) RXD (DATA OUTPUT) S1 S2 S3.
MSM80C154S/83C154S/85C154HVS 110 4.6.3.2 Mode 1 4.6.3.2.1 Outline Mode 1 is the 10-bit frame UART mode (with one start bit, eight data bits, and one stop bit) where the baud rate may be set to any value depending on the timer/counter 1 or timer/ counter 2 setting.
INTERNAL SPECIFICATIONS 111 B = f OSC × 65536-D RCAP2 1 × 16 1 2 1 × where B is the baud rate, f OSC the fundamental frequency (XTAL1·2), and D RCAP2 the contents of RCAP2L and RCAP2H (expressed in decimal).
MSM80C154S/83C154S/85C154HVS 112 4.6.3.2.5 Mode 1 UART error detection If the following two conditions are satisfied when the hexadecimal counter is in state 10 during reception of the stop bit, it is assumed that new data is received before processing of the previously received data has been completed.
INTERNAL SPECIFICATIONS 113 Figure 4-31 Serial port (mode 1) SBUF (R) INPUT SHIFT REG. INTERNAL BUS RI SBUF (T) START START INTERNAL BUS TI RXD SAMPLE LOGIC 1/16 COUTER TXD RXD WRITE TO SBUF SERIAL PO.
MSM80C154S/83C154S/85C154HVS 114 Figure 4-32 Serial port (mode 1) timing chart D1 WRITE TO SBUF TXD TERMINATE TRANSMISSION TX CLOCK TI D2 D3 D4 D5 D6 RX COUNTER RUN RXD SAMPLE CLOCK LOAD SBUF RXD SHIF.
INTERNAL SPECIFICATIONS 115 4.6.3.3 Mode 2 4.6.3.3.1 Outline Mode 2 is an 11-bit frame UART mode (with one start bit, eight data bits, one multipurpose data bit, and one stop bit) where the baud rate is 1/64th or 1/32nd of the fundamental oscillator (XTAL1·2) frequency.
MSM80C154S/83C154S/85C154HVS 116 When this “1” to “0” RXD change is detected, the hexadecimal counter which had been stopped in reset status commences to count up.
INTERNAL SPECIFICATIONS 117 SBUF (R) INPUT SHIFT REG. INTERNAL BUS RI START START SBUF (T) INTERNAL BUS TI RXD SAMPLE LOGIC 1/16 COUTER TXD RXD WRITE TO SBUF SERIAL PORT INTERRUPT REN SM2 RECEIVE DATA.
MSM80C154S/83C154S/85C154HVS 118 D1 WRITE TO SBUF TXD TERMINATE TRANSMISSION TX CLOCK TI D2 D3 D4 D5 D6 RX COUNTER RUN RXD SAMPLE CLOCK LOAD SBUF RXD SHIFT-IN CLOCK RI or SERR SET TERMINATE RECEPTION .
INTERNAL SPECIFICATIONS 119 4.6.3.4 Mode 3 4.6.3.4.1 Outline Mode 3 is another 11-bit frame UART mode (with one start bit, eight data bits, one multi- purpose data bit, and one stop bit).
MSM80C154S/83C154S/85C154HVS 120 B = f OSC × 65536-D RCAP2 1 × 16 1 2 1 × where B is the baud rate, f OSC the fundamental oscillator (XTAL1·2) frequency, and D RCAP2 the contents of R CAP2L and R CAP2H (expressed in decimal).
INTERNAL SPECIFICATIONS 121 If the above conditions are not satisfied when the hexadecimal counter is in state 10 during the multi-purpose data bit interval, the received data is disregarded, the SBUF, RB8, and RI flags remain unchanged, and the receive circuit is initialized when the hexadecimal counter is in state 10 during the stop bit interval.
MSM80C154S/83C154S/85C154HVS 122 SBUF (R) INPUT SHIFT REG. INTERNAL BUS RI SBUF (T) START START INTERNAL BUS TI RXD SAMPLE LOGIC 1/16 COUTER TXD RXD WRITE TO SBUF SERIAL PORT INTERRUPT REN SM2 RECEIVE.
INTERNAL SPECIFICATIONS 123 D1 WRITE TO SBUF TXD TERMINATE TRANSMISSION TX CLOCK TI D2 D3 D4 D5 D6 RX COUNTER RUN RXD SAMPLE CLOCK LOAD SBUF RXD SHIFT-IN CLOCK RI or SERR SET TERMINATE RECEPTION STOP .
MSM80C154S/83C154S/85C154HVS 124 4.6.4 Serial port application examples 4.6.4.1 I/O extension I/O extension can be achieved by using the serial port in mode 0. An input extension example is shown in Figure 4-37 and the corresponding timing chart is shown in Figure 4-38.
INTERNAL SPECIFICATIONS 125 An output extension example is shown in Figure 4-39 and the corresponding timing chart is shown in Figure 4-40. After output data has been written into SBUF and the output sequence completed, the latch pulse output from PX.
MSM80C154S/83C154S/85C154HVS 126 PX.X MSM80C154S MSM83C154S OUTPUT CONTROL PX.X INPUT CONTROL RXD TXD 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 8D 7D 6D 5D 4D 3D 2D 1D OC G 74LS373 QH QG QF QE QD QC QB QA CLK CK 74LS16.
INTERNAL SPECIFICATIONS 127 RXD TXD OUTPUT CONTROL INPUT CONTROL INPUT OUTPUT 74LS165 OUTPUT MSM80C154S/MSM83C154S OUTPUT In all examples, additional multiple bit I/O extension is made possible by multiple cascade connections of 74LS164 or 74LS165.
MSM80C154S/83C154S/85C154HVS 128 4.6.4.2 Multi-processor systems Multi-processor systems can be formed with MSM80C154S/MSM83C154S by using the serial port in mode 2 or mode 3 for inter-processor communications.
4.7 Interrupt 4.7.1 Outline MSM80C154S/MSM83C154S is equipped with six interrupts. 1. INT 0 External interrupt 0 2. TM0 Timer interrupt 0 3. INT 1 External interrupt 1 4.
MSM80C154S/83C154S/85C154HVS 130 Figure 4-44 Interrupt control equivalent circuit INTERRUPT REQUEST FLAG REGISTER INTERRUPT ENABLE REGISTER INTERRUPT PRIORITY REGISTER SOURCE ENABLE PX0 IP.0 PI NI EX0 IE.0 PT0 IP.1 PI NI EX0 IE.0 PX1 IP.2 PI NI EX0 IE.
INTERNAL SPECIFICATIONS 131 4.7.2 Interrupt enable register (IE) The function of the interrupt enable register (IE, 0A8H) is to enable or disable interrupt processes when an interrupt is requested.
MSM80C154S/83C154S/85C154HVS 132 4.7.3 Interrupt priority register (IP) The function of the interrupt priority register (IP, 0B8H) is to allocate rights to commence interrupt routines on a priority basis when an interrupt is requested.
INTERNAL SPECIFICATIONS 133 4.7.3.1 Priority interrupt routine flow The flow of interrupt processing when a priority interrupt is generated and processed after a routine has been commenced by a non-priority interrupt generated during execution of a main routine program is outlined in Figure 4-45 below.
MSM80C154S/83C154S/85C154HVS 134 4.7.3.2 Interrupt routine flow when priority circuit is stopped When bit 7 (PCT) of the priority register (IP 0B8H) is set to “1”, all interrupt control is transferred to the interrupt enable register (IE 0A8H).
INTERNAL SPECIFICATIONS 135 4.7.3.3 Interrupt priority when priority register (IP) contents are all “0” The interrupt priority when the priority register (IP, 0B8H) contents are all “0” indicates the priority in which a certain interrupt is processed in preference to other interrupts when interrupt requests are generated simultaneously.
MSM80C154S/83C154S/85C154HVS 136 4.7.4 Detection of external interrupt signals INT 0 and INT 1 4.7.4.1 Outline of INT signal detection Detect modes of the external interrupt signals 0 and 1 can be set to level-detect or trigger- detect mode by the IT0 and IT1 data values in the timer control register (TCON 88H) as indicated in Table 4-22.
INTERNAL SPECIFICATIONS 137 4.7.4.3 External interrupt signal 0 and 1 trigger detection When bit 0 (IT0) in the timer Control register (TCON 88H) is “1”, external interrupt 0 is edge- activated. And when bit 2 (IT1) is “1”, external interrupt 1 is also edge-activated.
MSM80C154S/83C154S/85C154HVS 138 4.7.5 MSM80C154S/MSM83C154S interrupt response time charts 4.7.5.1 Interrupt response time chart when interrupt conditions are satisfied during execution of ordinary i.
INTERNAL SPECIFICATIONS 139 S4 S5 S6 S1 S2 S3 XTAL1 ALE Timer flag 1 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 Instruction execution S6 1 - 0 1 0 - M1~M4 M1 or M2 M1~M4 M1 or M2 M1 M2 1 - .
MSM80C154S/83C154S/85C154HVS 140 4.7.5.2 Interrupt response time chart when interrupt conditions are satisfied during execution of IE or IP register operation instruction in main routine If interrupt .
INTERNAL SPECIFICATIONS 141 S4 S5 S6 S1 S2 S3 XTAL1 ALE Timer flag 1 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 Instruction execution S6 1 - 0 1 0 - M1 or M2 M1~M4 M1 or M2 M1 M2 1 - 0 Exec.
MSM80C154S/83C154S/85C154HVS 142 4.7.5.3 Interrupt response time chart when an ordinary instruction is executed after temporarily returning to the main routine from continuous interrupt processing If .
INTERNAL SPECIFICATIONS 143 Figure 4-51 Interrupt response time chart when ordinary instruction is executed after returning to main routine during continuous interrupt processing S4 S5 S6 S1 S2 S3 XTA.
MSM80C154S/83C154S/85C154HVS 144 4.7.5.4 Interrupt response time chart when an IE or IP manipulating instruction is executed after temporarily returning to the main routine from continuous interrupt p.
INTERNAL SPECIFICATIONS 145 Figure 4-52 Interrupt response time chart when IE or IP manipulating instruction is executed after returning to main routine during continuous interrupt processing S4 S5 S6.
MSM80C154S/83C154S/85C154HVS 146 4.8 CPU “Power Down” 4.8.1 Outline Since the internal MSM80C154S/MSM83C154S circuits have been designed as completely static circuits, all internal information (register data) is preserved if XTAL1·2 oscillation is stopped.
INTERNAL SPECIFICATIONS 147 XTAL 2 XTAL 1 TIMER, S-I/O & INTERRUPT CPU CONTROL CLOCK Bit Set SMOD HPD RPD — GF1 GF0 PD IDL 76543210 *• PCON, 87H CONTROL Figure 4-53 ldle mode equivalent circui.
MSM80C154S/83C154S/85C154HVS 148 Table 4-23 CPU pin details in idle mode Name Internal ROM External ROM P1.0/T2 Port data output Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.3 Port data output Port data output P1.
INTERNAL SPECIFICATIONS 149 Figure 4-54 Idle mode setting time chart (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSE.
MSM80C154S/83C154S/85C154HVS 150 Figure 4-55 Idle mode setting time chart (external ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 .
INTERNAL SPECIFICATIONS 151 4.8.3 Soft power down mode (PD) setting Soft power down mode (PD) is set when “1” is set in bit 1 (PD) of the power control register (PCON 87H).
MSM80C154S/83C154S/85C154HVS 152 XTAL 2 XTAL 1 CPU CLOCK Bit Set SMOD HPD RPD — GF1 GF0 PD IDL 76543210 *• CONTROL PCON 87H IOCON 0F8H I/O FLOATING Bit Set — T32 SERR IZC P3HZ P2HZ P1HZ ALF 7654.
INTERNAL SPECIFICATIONS 153 Q S R IE0 or 1 Q D L INT 0 or INT 1 PD S3 RESET S6 M END PCON5(RPD) PDRESET S5 Figure 4-57 Power down cancellation circuit at INTERRUPT level input S4 S2 S3 Q S L R IE0 or .
MSM80C154S/83C154S/85C154HVS 154 S3 Q D L Q D R F/F1 F/F2 S5 T0 or T1 V CC RESET PD F/F1 F/F2 PCON5(RPD) Q S R TF0 or 1 PDRESET RESET TIMER0, 1 C Figure 4-59 TIMER0, 1 power down cancellation circuit.
INTERNAL SPECIFICATIONS 155 Table 4-24 CPU pin details (ALF=0) in soft power down mode (PD) Name Internal ROM External ROM P1.0/T2 Port data output Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.
MSM80C154S/83C154S/85C154HVS 156 S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W-PCON 1 0 *PCON-bit 1 1 0 SOFT POWER DOWN MODE S6 PORT DATA PORT DATA PD .
INTERNAL SPECIFICATIONS 157 Figure 4-61 Soft power down mode setting time chart (external ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W-P.
MSM80C154S/83C154S/85C154HVS 158 Table 4-25 CPU pin details (ALF=1) in soft power down mode (PD) Name Internal ROM External ROM P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET P3.0/RXD P3.1/TXD P3.2/ INT 0 P3.3/ INT 1 P3.4/ T0 P3.5/ T1/HPDI P3.6/ WR P3.
INTERNAL SPECIFICATIONS 159 Figure 4-62 Soft power down mode setting and I/O floating time chart (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN *PORT 0 PORT 1 1 0 PORT 2 1 0 .
MSM80C154S/83C154S/85C154HVS 160 Figure 4-63 Soft power down mode setting and I/O floating time chart (external ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 .
INTERNAL SPECIFICATIONS 161 4.8.4 Hard power down mode (HPD) setting To set hard power down mode (HPD), “1” is set in bit 6 (HPD) of the power control register (PCON 87H) in advance to attain the circuit connections shown in Figure 4-61.
MSM80C154S/83C154S/85C154HVS 162 Figure 4-64 Hard power down mode equivalent circuit XTAL 2 XTAL 1 CPU CLOCK Bit Set SMOD HPD RPD — GF1 GF0 PD IDL 76543210 •• CONTROL PCON 87H IOCON 0F8H I/O FLO.
INTERNAL SPECIFICATIONS 163 Table 4-26 CPU pin details (ALF=0) in hard power down mode (HPD) Name Internal ROM External ROM P1.0/T2 Port data output Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.
MSM80C154S/83C154S/85C154HVS 164 Figure 4-65 Hard power down mode setting time chart (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 *HPDI [P3.
INTERNAL SPECIFICATIONS 165 Figure 4-66 Hard power down mode setting time chart (external ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 *HPDI [P3.
MSM80C154S/83C154S/85C154HVS 166 Table 4-27 CPU pin details (ALF=1) in hard power down mode (HPD) Name Internal ROM External ROM P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET P3.0/RXD P3.1/TXD P3.2/ INT 0 P3.3/ INT 1 P3.4/ T0 P3.5/ T1/HPDI P3.
INTERNAL SPECIFICATIONS 167 Figure 4-67 Hard power down mode setting and I/O floating time chart (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 P.
MSM80C154S/83C154S/85C154HVS 168 Figure 4-68 Hard power down mode setting andl/Of loating time chart (external ROM mode) S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 PORT 2 PORT 3 PCON-bit 6 1 0 HARD POWER DOWN MODE S6 HPD SET CYCLE 1 0 1 0 IOCON-bit 0 *ALF=“1” S1 *HPDI [P3.
INTERNAL SPECIFICATIONS 169 4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation) 4.9.1 Outline CPU power down mode (IDLE, PD, and HPD) can be cancelled (CPU activation) in the following two ways. The CPU is reset when a “1” reset signal is applied to the CPU RESET pin, and the program is executed from address 0.
MSM80C154S/83C154S/85C154HVS 170 Figure 4-69 Restart from idle mode by reset (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 → M2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1.
INTERNAL SPECIFICATIONS 171 Figure 4-70 Restart from idle mode by reset (external ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE S6 1 0 PSEN 1.
MSM80C154S/83C154S/85C154HVS 172 Figure 4-71 Restart from soft power mode by reset (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 → M2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0.
INTERNAL SPECIFICATIONS 173 Figure 4-72 Restart from soft power mode by reset (external ROM mode) S1 S2 S3 S4 S5 S6 M1 → M2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE .
MSM80C154S/83C154S/85C154HVS 174 Figure 4-73 Restart from hard power down mode by reset (internal ROM mode) S1 S2 S3 S4 S5 S6 M1 → M2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL.
INTERNAL SPECIFICATIONS 175 Figure 4-74 Restart from hard power down mode by reset (external ROM mode) S1 S2 S3 S4 S5 S6 M1 → M2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0.
MSM80C154S/83C154S/85C154HVS 176 4.9.3 Cancellation of CPU power down mode (IDLE, PD) by interrupt signal When idle mode (IDLE) and soft power down mode (PD) are cancelled by interrupt signal, power down mode cancellation condition is determined by bit 5 (RPD) of the power control register (PCON 87H) shown in Table 4-29.
INTERNAL SPECIFICATIONS 177 Figure 4-75 Equivalent circuit for, DLE and PD mode rancellation by interrupt signal IE0 [TCON.1] IE.0 TF0 [TCON.5] IE.1 IE1 [TCON.
MSM80C154S/83C154S/85C154HVS 178 Figure 4-76 Restart from idle mode by interrupt INT 0 or 1 (internal ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1.
INTERNAL SPECIFICATIONS 179 Figure 4-77 Restart from idle mode by interrupt INT 0 or 1 (external ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1 0 AL.
MSM80C154S/83C154S/85C154HVS 180 Figure 4-78 Restart from soft power down mode by Interrupt INT 0 or 1 (internal ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1.
INTERNAL SPECIFICATIONS 181 Figure 4-79 Restart from soft power down mode by interrupt INT 0 or 1 (external ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL.
MSM80C154S/83C154S/85C154HVS 182 4.9.3.2 Cancellation of CPU power down mode (IDLE, PD) by interrupt request signal and restart from next address of stop address To cancel idle mode (IDLE) or soft pow.
INTERNAL SPECIFICATIONS 183 Figure 4-81 Restart from idle mode by INT 0 or 1 (internal ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1 0 ALE S6 1 0 P.
MSM80C154S/83C154S/85C154HVS 184 Figure 4-82 Restart from idle mode by INT 0 or 1 (external ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1 0 ALE S6 .
INTERNAL SPECIFICATIONS 185 Figure 4-83 Restart from soft power down mode by INT 0 or 1 (internal ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT .
MSM80C154S/83C154S/85C154HVS 186 Figure 4-84 Restart from soft power down mode by INT 0 or 1 (external ROM mode) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 .
INTERNAL SPECIFICATIONS 187 4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode Figures 4-85-1/2 and 2/2 show the examples of the MSM80C154S/83C154S battery backup circuits with hard power down mode. The hard power down mode serves to retain data stored in the CPU and external RAM if the AC 100V power failure occurs.
MSM80C154S/83C154S/85C154HVS 188 Figure 4-85-1/2 MSM80C154S/83C154S battery back up with hard power down mode RD WR P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 EA PSEN P1 P3 XTAL1 XTAL2 V CC V SS RESET T1(P3.5) 10PF 1000 µ F 0.
INTERNAL SPECIFICATIONS 189 Figure 4-85-2/2 MSM80C154S/83C154S battery back up with hard power down mode VCB P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 CS7 CS0 P2.
MSM80C154S/83C154S/85C154HVS 190 5. INPUT/OUTPUT POR TS.
INPUT/OUTPUT PORTS 191.
MSM80C154S/83C154S/85C154HVS 192 5. INPUT/OUTPUT PORTS 5.1 Outline MSM80C154S/MSM83C154S is equipped with four 8-bit input/output ports. The functions of these four ports (port 0, 1, 2, and 3) are listed below. 1) Port 0: Input/output bus port, address output port, and data input/output port.
INPUT/OUTPUT PORTS 193 Q D MODIFY READ INTERNAL BUS N PORT 0 WPO Figure 5-2 Port 0 input/Output port equivalent circuit in internal ROM mode PC0~7 RA0~7 ACC0~7 READ INTERNAL BUS N P V CC PORT 0 Figure.
MSM80C154S/83C154S/85C154HVS 194 PORT0 Accumulator bit Address 1 P0.0 ACC.0 PC RA –0 2 P0.1 ACC.1 PC RA –1 3 P0.2 ACC.2 PC RA –2 4 P0.3 ACC.3 PC RA –3 5 P0.
INPUT/OUTPUT PORTS 195 5.3 Port 1 Port 1 is a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-4. A “quasi-bidirectional port” refers to a port which has internal pull-up resistance when used as an input port.
MSM80C154S/83C154S/85C154HVS 196 Q D READ INTERNAL BUS WP1 MODIFY Q D C CONTROL P1 V CC P2 P3 PORT 1 N Figure 5-4 Port 1 internal equivalent circuit.
INPUT/OUTPUT PORTS 197 READ N OFF P3 ON R=100k Ω . . P2 ON R=10k Ω . . P1 ON R=500 Ω . . V CC INTERNAL BUS I OH (A) When accelerator circuit is activated READ N OFF P3 ON R=100k Ω . . P2 ON R=10k Ω . . P1 OFF R=500 Ω . . V CC INTERNAL BUS I OH (B) When "1" data is held OFF READ N ON P3 R=100k Ω .
MSM80C154S/83C154S/85C154HVS 198 Figure 5-6 Quasi-bidirectional port accelerator circuit operation time chart S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 XTAL1 1- 0- ALE 1- 0- W-PORT 1- 0 PORT-OUT 1- 0 .
INPUT/OUTPUT PORTS 199 READ N OFF P2 ON R=10k Ω . . V CC INTERNAL BUS (A) "1" data writing equivalent circuit P3 ON R=100k Ω . . READ N OFF P2 ON R=10k Ω . . V CC INTERNAL BUS (B) "1" data input equivalent circuit P3 ON R=100k Ω .
MSM80C154S/83C154S/85C154HVS 200 PORT1 Function P1.0 T2 [TIMER COUNTER 2 EXTERNAL CLOCK] P1.1 T2EX [TIMER COUNTER 2 EXTERNAL CONTROL] Table 5-2 Port 1 CPU control pin table Table 5-3 Port 1 pin table PORT1 Accumulator bit 1 P1.0 ACC.0 2 P1.1 ACC.1 3 P1.
INPUT/OUTPUT PORTS 201 5.4 Port 2 Port 2 can function as a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-8. It can also be used for output of addresses 8 thru 15 in external ROM and external RAM (using DPTR) modes.
MSM80C154S/83C154S/85C154HVS 202 PC/DATA P1 V CC P2 P3 PORT 2 N PC8~15 RA8~15 (DPH) Figure 5-9 Port 2 address output equivalent circuit for external memory Table 5-4 Port 2 pin table PORT2 Accumulator bit Address 1 P2.0 ACC.0 PC RA –8 2 P2.1 ACC.1 PC RA –9 3 P2.
INPUT/OUTPUT PORTS 203 5.5 Port 3 Port 3 can function as a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-10, and can also be used as a CPU control pin. When port 3 is used as a quasi-bidirectional port, all functions are identical to those described for port 1.
MSM80C154S/83C154S/85C154HVS 204 Table 5-5 Port 3 CPU control pin function table PORT3 PORT 3 PIN ALTERNATE FUNCTION P3.0 RXD [SERIAL INPUT PORT] P3.1 TXD [SERIAL OUTPUT PORT] P3.2 INT 0 [EXTERNAL INTERRUPT 0] P3.3 INT 1 [EXTERNAL INTERRUPT 1] P3.4 T0 [TIMER/COUNTER 0 CLOCK] P3.
INPUT/OUTPUT PORTS 205 5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD) The port 0, 1, 2, and 3 output status can be set to either data output or floating when MSM80C154S/MSM83C154S is in power down mode (PD, HPD).
MSM80C154S/83C154S/85C154HVS 206 Bit Set — T32 SERR IZC P3HZ P2HZ P1HZ ALF 76543210 ••••• [IOCON 0F8H] Q D READ INTERNAL BUS W PORT MODIFY P2-10k Ω V CC P3-100k Ω I/O N PORT1, 2, 3 POW.
INPUT/OUTPUT PORTS 207 5.7 High Impedance Input Port Setting of Each Ouasi-bidirectional Port 1, 2, and 3 Each of the quasi-bidirectional input ports 1, 2, and 3 can be set as high impedance input ports.
MSM80C154S/83C154S/85C154HVS 208 5.9 Precautions When Driving External Transistors by Ouasi-bidirectional Port Output Signals The following points must be carefully considered when quasi-bidirectional ports are used to drive a transistor by the circuit shown in Figure 5-12.
INPUT/OUTPUT PORTS 209 V CC 10k Ω I B V CC P 100k Ω OUT CPU "1" OUT Figure 5-13 Drive circuit for NPN transistor by level shifter I B V CC OUT CPU "0" OUT Figure 5-14 PNP trans.
MSM80C154S/83C154S/85C154HVS 210 5.10 Port Output Timing 1) One machine cycle instruction output timing S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 XTAL1 1 0 ALE 1 0 W-PORT 1 0 PORT-OUT 1 0 PORT NEW DAT.
INPUT/OUTPUT PORTS 211 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 XTAL1 1 0 ALE 1 0 W-PORT 1 0 PORT-OUT 1 0 PORT NEW DATA M2 PORT OLD DATA 2M CYCLE OP MOV data address, # data ORL data address, # data .
MSM80C154S/83C154S/85C154HVS 212 5.11 Port Data Manipulating Instructions The MSM80C154S/MSM83C154S port operation instructions for ports 0, 1, 2, and 3 are divided into two groups-one where external .
INPUT/OUTPUT PORTS 213.
MSM80C154/83C154/85C154 214 6. ELECTRICAL CHARACTERISTICS.
ELECTRICAL CHARACTERISTICS 215.
MSM80C154/83C154/85C154 216 6. ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Parameter Supply voltage Input voltage Storage temperature Symbol V CC V I T stg Ta=25°C Ta=25°C — Conditions –0.5~7 –0.5~V CC +0.5 –55~+150 Rating V V °C Unit 6.
ELECTRICAL CHARACTERISTICS 217 6.3 DC Characteristics 1 (V CC =4.0 to 6.0V,V SS =0V, Ta=–40 ° C to +85 ° C) Parameter Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage [PO.
MSM80C154/83C154/85C154 218 V CC Freq. 1MHz 3MHz 12MHz 16MHz 4V 2.2 3.7 12.0 16.0 5V 3.1 5.2 16.0 20.0 6V 4.1 7.0 20.0 25.0 Maximum Power Supply Current Normal Operation I CC (mA) V CC Freq. 24MHz 4.5V 25.0 5V 29.0 6V 35.0 V CC Freq. 1MHz 3MHz 12MHz 16MHz 4V 0.
ELECTRICAL CHARACTERISTICS 219 DC Characteristics 2 — Output High Voltage V OH1 I OH =–20 m A 0.75 V CC —V (PORT 0, ALE, PSEN ) –40 Logical 0 Input Current/ Logical 1 Output Current/ (PORT 1, 2, 3) I IL / I OH V I =0.1 V –5 — m A V O =0.1 V –300 Logical 1 to 0 Transition I TL V I =1.
MSM80C154/83C154/85C154 220 V CC V SS INPUT OUTPUT Note 3 V AI O Note 2 V IH V IL 12 34 V CC V SS INPUT OUTPUT Note 3 V A Note 2 V IH V IL V CC V SS INPUT OUTPUT V Note 1 V CC V SS INPUT OUTPUT Note 3 V IH V IL A A Note 1 : Repeated for specified input pins.
ELECTRICAL CHARACTERISTICS 221 6.4 External Program Memory Access AC Characteristics V CC =2.2 to 6.0V, V SS =0V, Ta=–40 ° C to +85 ° C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load Parameter Symble Unit Min. Max.
MSM80C154/83C154/85C154 222 External program memory read cycle tLHLL tA VLL tLLPL tPLPH tLLIV tPLIV tLLAX tAZPL tPXIX tPXIZ tPXA V tA VIV A0~A7 INSTR IN A0~A7 PO RT 0 A8~A15 A0~A7 PORT 2 A8~A15 ALE PS.
ELECTRICAL CHARACTERISTICS 223 6.5 External Data Memory Access AC Characteristics VCC=2.2 to 6.0V, VSS=0V, Ta=–40 ° C to +85 ° C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load Parameter Symbol Unit Min. Max. 1 to 24 MHz Variable clock from 45.
MSM80C154/83C154/85C154 224 External data memory read cycle External data memory write cycle tLHLL tLLDV tLL WL tRLRH tA VLL tRHDX tRHDZ tA VDV A0~A7 RrorDPL DA T A IN PO RT 0 P2.
ELECTRICAL CHARACTERISTICS 225 6.6 Serial Port (I/O Extension Mode) AC Characteristics V CC =2.2 to.0V, V SS =0V, Ta=–40 ° C to 85 ° C Parameter Serial Port Clock Cycle T ime Output Data Setup to .
MSM80C154/83C154/85C154 226 VALID ALE SHIFT CLOCK INPUT DATA MACHINE CYCLE OUTPUT DATA tXLXL tQVXH tXHQX tXHDV tXHDX VALID VALID VALID VALID VALID VALID VALID.
ELECTRICAL CHARACTERISTICS 227 6.7 AC Characteristics Measuring Conditions 1. Input/output signal V IH V IL V IH V IL V OH V OL TEST POINT V OH V OL * The input signals in AC test mode are either V OH (logic “1”) orV OL (logic “0”). Timing measurements are made atV IH (logic “1”) and V IL (10gic “0”).
MSM80C154/83C154/85C154 228 6.8 XTAL1 External Clock Input Waveform Conditions P arameter Oscillator F req. High Time Low Time Rise Time F all Time Symbol 1/tCLCL tCHCX tCLCX tCLCH tCHCL Min 0 15 15 — — Max 24 — — 5 5 Unit MHz ns ns ns ns tCHCX tCHCL tCHCX tCLCH tCLCL 0.
7. DESCRIPTION OF INSTR UCTIONS.
MSM80C154S/83C154S/85C154HVS 230.
DESCRIPTION OF INSTRUCTIONS 231 7. DESCRIPTION OF INSTRUCTIONS 7.1 Outline MSM80C154S/MSM83C154S is a microcontroller designed for parallel processing in an 8-bit ALU.
MSM80C154S/83C154S/85C154HVS 232 7.2 Description of Instruction Symbols The instruction symbols have the following meanings. A Accumulator AB Register pair AC Auxiliary carry B Arithmetic operation register C Carry (the bit 7 carry represented by CY is changed to C in Chapter 7.
DESCRIPTION OF INSTRUCTIONS 233 7.3 List of Instructions MSM80C154S/MSM83C154S instruction table 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 111.
MSM80C154S/83C154S/85C154HVS 234 7.4 Simplified Description of Instructions Note that “data address” is represented as “direct address” in this description.
DESCRIPTION OF INSTRUCTIONS 235 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Accumulator operation instructions CLR CPL RL RLC RR RRC SWAP A A A A A A.
MSM80C154S/83C154S/85C154HVS 236 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Increment & decrement instructions Logical operation instructions IN.
DESCRIPTION OF INSTRUCTIONS 237 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Immediate data setting instructions Logical operation instructions ORL OR.
MSM80C154S/83C154S/85C154HVS 238 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Bit transfer instructions Carry flag operation instructions Immediate da.
DESCRIPTION OF INSTRUCTIONS 239 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Data transfer instructions Bit manipu- lation instructions Constant value.
MSM80C154S/83C154S/85C154HVS 240 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Subroutine instructions Data exchange instructions XCH XCH XCH XCHD PUSH.
DESCRIPTION OF INSTRUCTIONS 241 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Subroutine instructions Jump instructions Branching instructions RETI AJM.
MSM80C154S/83C154S/85C154HVS 242 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Branching instructions CJNE CJNE A, #data, rel Rr,#data,rel 3 3 2 2 (PC).
DESCRIPTION OF INSTRUCTIONS 243 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Branching instructions CJNE DJNZ DJNZ JZ @Rr, #data, rel Rr, rel direct, .
MSM80C154S/83C154S/85C154HVS 244 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation Branching instructions JNZ rel 2 2 (PC) ← (PC)+2 IF (A) ≠ 0 THEN (PC.
DESCRIPTION OF INSTRUCTIONS 245 Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page Classifi- cation External memory instructions Other instruction MOVX A, @Rr (A) ← ((Rr)).
MSM80C154S/83C154S/85C154HVS 246 7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions Note: “direct address” is represented as “data address” in this detailed description.
DESCRIPTION OF INSTRUCTIONS 247 2. ADD A, #data (Add immediate data) 00100100 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Description Example ADD A, #07H Instructi.
MSM80C154S/83C154S/85C154HVS 248 3. ADD A, @Rr (Add indirect address) 0010011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example ADD A, @R0 Instruction co.
DESCRIPTION OF INSTRUCTIONS 249 4. ADD A, Rr (Add register) 00101 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example ADD A, R6 Instruction code : Byte 1 (A) ← (A)+(Rr) r=0 thru 7 : C AC F0 RS1 RS0 OV F1 P •• • • : : : The register r contents are added to the accumulator.
MSM80C154S/83C154S/85C154HVS 250 5. ADD A, data address (Add memory) 00100101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description Example ADD A, P1 Inst.
DESCRIPTION OF INSTRUCTIONS 251 6. ADDC A, #data (Add carry plus immediate data to accumulator) 00110100 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Description Ex.
MSM80C154S/83C154S/85C154HVS 252 7. ADDC A, @Rr (Add carry plus indirect address to accumulator) 0011011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Exampl.
DESCRIPTION OF INSTRUCTIONS 253 8. ADD A, Rr (Add carry plus register to accumulator) 00111 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example A.
MSM80C154S/83C154S/85C154HVS 254 9. ADDC A, data address (Add carry plus memory to accumulator) 00110101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Descrip.
DESCRIPTION OF INSTRUCTIONS 255 10. AJMP code address (Absolute jump within 2K byte page) A 10 A 9 A 8 00001 70 Instruction code Call address Operations Number of bytes Number of cycles Flags (PSW) De.
MSM80C154S/83C154S/85C154HVS 256 11. ANL A, #data (Logical AND immediate data to accumulator) 01010100 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Description Exam.
DESCRIPTION OF INSTRUCTIONS 257 12. ANL A, @Rr (Logical AND indirect address to accumulator) 0101011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example AN.
MSM80C154S/83C154S/85C154HVS 258 13. ANL A, Rr (Logical AND register to accumulator) 01011 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example AN.
DESCRIPTION OF INSTRUCTIONS 259 14. ANL A, data address (Logical AND memory to accumulator) 01010101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description.
MSM80C154S/83C154S/85C154HVS 260 15. ANL C, bit address (Logical AND bit to carry flag) 10000010 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example ANL C, ACC.
DESCRIPTION OF INSTRUCTIONS 261 16. ANL C,/bit address (Logical AND complement bit to carry flag) 10110000 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example ANL C,/P1.
MSM80C154S/83C154S/85C154HVS 262 17. ANL data address, #data (Logical AND immediate data to memory) 01010011 70 Instruction code Data address #data Operation Number of bytes Number of cycles Flags (PS.
DESCRIPTION OF INSTRUCTIONS 263 18. ANL data address, A (Logical AND accumulator to memory) 01010010 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description.
MSM80C154S/83C154S/85C154HVS 264 19. CJNE @Rr, #data, code address (Compare indirect address to immediate data, jump if not equal) 1011011 r 70 Instruction code #data Relative offset Operations Number.
DESCRIPTION OF INSTRUCTIONS 265 Instruction code CJNE @R1, #05H, TEST Example 10110111 70 Byte 1 Register 1 00110101 70 Before execution Register 1 00110101 70 After execution : 35H 00101011 70 35H 00.
MSM80C154S/83C154S/85C154HVS 266 20. CJNE A, #data, code address (Compare immediate data to accumulator, jump if not equal) 10110100 70 Instruction code #data Relative offset Operations Number of byte.
DESCRIPTION OF INSTRUCTIONS 267 Instruction code CJNE A, #0AH, SS1 Example 10110100 70 Byte 1 Accumulator 01010000 70 Before execution Accumulator 01010000 70 After execution : 1 Carry flag 0 Carry fl.
MSM80C154S/83C154S/85C154HVS 268 21. CJNE A, data address, code address (Compare memory to accumulator, jump if not equal) 10110101 70 Instruction code Data address Relative offset Operations Number o.
DESCRIPTION OF INSTRUCTIONS 269 Instruction code CJNE A, 50H, NEXT Example 10110101 70 Byte 1 50H 01011110 70 Before execution 50H 01011110 70 After execution : 0 Carry flag 1 Carry flag Program count.
MSM80C154S/83C154S/85C154HVS 270 22. CJNE Rr, #data, code address (Compare immediate data to register, jump if not equal) 10111 r 2 r 1 r 0 70 Instruction code #data Relative offset Operations Number .
DESCRIPTION OF INSTRUCTIONS 271 Instruction code CJNE R4, #32H, COUNT Example 10111100 70 Byte 1 Register 4 00000001 70 Before execution Register 4 00000001 70 After execution : 1 Carry flag 1 Carry f.
MSM80C154S/83C154S/85C154HVS 272 23. CLR A (Clear accumulator) 11100100 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example CLR A Instruction code : Byte 1 (A) ← 0 : C AC F0 RS1 RS0 OV F1 P • : : : The accumulator is cleared to 0 and flag is updated.
DESCRIPTION OF INSTRUCTIONS 273 24. CLR C (Clear carry flag) 11000011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example CLR C Instruction code : Byte 1 (C) ← 0 : C AC F0 RS1 RS0 OV F1 P • : : : The carry flag is cleared to 0.
MSM80C154S/83C154S/85C154HVS 274 25. CLR bit address (Clear bit) 11000010 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example CLR P1.
DESCRIPTION OF INSTRUCTIONS 275 26. CPL A (Complement accumulator) 11110100 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example CPL A Instruction code : Byte 1 (A) ← ( A ) : C AC F0 RS1 RS0 OV F1 P : : : Accumulator data 0 is set to 1 and 1 is set to 0.
MSM80C154S/83C154S/85C154HVS 276 27. CPL C (Complement carry flag) 10110011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example CPL C Instruction code : Byte 1 (C) ← ( C ) : C AC F0 RS1 RS0 OV F1 P • : : : The carry flag is set to 1 if 0, set to 0 if 1.
DESCRIPTION OF INSTRUCTIONS 277 28. CPL bit address (Complement bit) 10110010 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example CLR B.
MSM80C154S/83C154S/85C154HVS 278 29. DA A (Decimal adjust accumulator) 11010100 70 Instruction code Operations Number of bytes Number of cycles Flags (PSW) Description : Byte 1 10 1 +6 (C) ← 1 : C A.
DESCRIPTION OF INSTRUCTIONS 279 Example DA A Instruction code 11010100 70 Byte 1 Accumulator 10110101 70 Before execution Accumulator 00010101 70 After execution : 0 C 1 C 0 AC 0 AC Accumulator 001100.
MSM80C154S/83C154S/85C154HVS 280 30. DEC @Rr (Decrement indirect address) 0001011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example DEC @R0 Instruction c.
DESCRIPTION OF INSTRUCTIONS 281 31. DEC A (Decrement accumulator) 00010100 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example DEC A Instruction code : Byte 1 (A) ← (A)–1 : C AC F0 RS1 RS0 OV F1 P • : : : The accumulator contents are decremented by 1, and the flag is updated.
MSM80C154S/83C154S/85C154HVS 282 32. DEC Rr (Decrement register) 00011 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example DEC R7 Instruction code : Byte 1 (Rr) ← (Rr)–1 r=0 thru 7 : C AC F0 RS1 RS0 OV F1 P : : : The register r contents are decremented by 1.
DESCRIPTION OF INSTRUCTIONS 283 33. DEC data address (Decrement memory) 00010101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description Example DEC 5AH Ins.
MSM80C154S/83C154S/85C154HVS 284 34. DIV AB (Divide accumulator by B) 10000100 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example DIV AB(0AEH÷7H=18 ……�.
DESCRIPTION OF INSTRUCTIONS 285 35. DJNZ Rr, code address (Decrement register, and jump if not zero) 11011 r 2 r 1 r 0 70 Instruction code Relative offset Operations Number of bytes Number of cycles F.
MSM80C154S/83C154S/85C154HVS 286 Instruction code DJNZ R1, LOOP Example 11011001 70 Byte 1 Register 1 00001000 70 Before execution Register 1 00000111 70 After execution : Program counter 15 8 0000000.
DESCRIPTION OF INSTRUCTIONS 287 36. DJNZ data address, code address (Decrement memory, and jump if not zero) 11010101 70 Instruction code Data address Relative offset Operations Number of bytes Number.
MSM80C154S/83C154S/85C154HVS 288 Instruction code DJNZ 57H, LOOP 1 Example 11010101 70 Byte 1 57H 01101011 70 Before execution 57H 01101010 70 After execution : Program counter 15 8 0001000010010101 7.
DESCRIPTION OF INSTRUCTIONS 289 37. INC @Rr (Increment indirect address) 0000011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example INC @R1 Instruction co.
MSM80C154S/83C154S/85C154HVS 290 38. INC A (Increment accumulator) 00000100 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example INC A Instruction code : Byte 1 (A) ← (A)+1 : C AC F0 RS1 RS0 OV F1 P • : : : The accumulator contents are incremented by 1, and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 291 39. INC DPTR (Increment data pointer) 10100011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example INC DPTR Instruction code : Byte 1 (DPTR) ← (DPTR)+1 : C AC F0 RS1 RS0 OV F1 P : : : 16-bit contents od the data pointer (DPH·DPL) are incremented by 1.
MSM80C154S/83C154S/85C154HVS 292 40. INC Rr (Increment register) 00001 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example INC R5 Instruction code : Byte 1 (Rr) ← (Rr)+1 r=0 thru 7 : C AC F0 RS1 RS0 OV F1 P : : : The register r contents are incremented by 1.
DESCRIPTION OF INSTRUCTIONS 293 41. INC data address (Increment memory) 00000101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description Example INC P1 Inst.
MSM80C154S/83C154S/85C154HVS 294 42. JB bit address, code address (Jump if bit is set) 00100000 70 Instruction code Bit address Relative offset Operations Number of bytes Number of cycles Flags (PSW) .
DESCRIPTION OF INSTRUCTIONS 295 Instruction code JB 34.3, ENTER Example 00100000 70 Byte 1 34 0100 1000 70 Before execution 34 0100 1000 70 After execution : Program counter 15 8 0000100100000011 70 Program counter 15 8 0000100101010000 70 00010011 70 Byte 2 01001010 70 Byte 3 LOC 0903 0950 OBJ 20134A ACA0 SOURCE BITTS:JB 34.
MSM80C154S/83C154S/85C154HVS 296 43. JBC bit address, code address (Jump and clear if bit is set) 00010000 70 Instruction code Bit address Relative offset Operations Number of bytes Number of cycles F.
DESCRIPTION OF INSTRUCTIONS 297 Instruction code JBC 46.1, COUNT 4 Example 00010000 70 Byte 1 46 101010 10 70 Before execution 46 101010 00 70 After execution : Program counter 15 8 0000000100110110 70 Program counter 15 8 0000000011011100 70 01110001 70 Byte 2 10100011 70 Byte 3 LOC 00DC 0136 OBJ C281 1071A3 SOURCE COUNT 4:CLR 128.
MSM80C154S/83C154S/85C154HVS 298 44. JC code address (Jump if carry is set) 01000000 70 Instruction code Relative offset Operations Number of bytes Number of cycles Flags (PSW) Description : Byte 1 (P.
DESCRIPTION OF INSTRUCTIONS 299 Instruction code JC CARRY Example 01000000 70 Byte 1 Before execution After execution : Program counter 15 8 0001011011011110 70 Program counter 15 8 0001011011110101 7.
MSM80C154S/83C154S/85C154HVS 300 45. JMP @A + DPTR (Jump to sum of accumulator and data pointer) 01110011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example.
DESCRIPTION OF INSTRUCTIONS 301 46. JNB bit address, code address (Jump if bit is not set) 00110000 70 Instruction code Bit address Relative offset Operations Number of bytes Number of cycles Flags (P.
MSM80C154S/83C154S/85C154HVS 302 Instruction code JNB 37.3, EXIT Example 00110000 70 Byte 1 37 0011 0111 70 Before execution 37 0011 0111 70 After execution : Program counter 15 8 0000100000110101 70 Program counter 15 8 0000100001011010 70 00101011 70 Byte 2 00100010 70 Byte 3 LOC 0835 085A OBJ 302B22 E6 SOURCE TEST:JNB 37.
DESCRIPTION OF INSTRUCTIONS 303 47. JNC code address (Jump if carry is not set) 01010000 70 Instruction code Relative offset Operations Number of bytes Number of cycles Flags (PSW) Description : Byte .
MSM80C154S/83C154S/85C154HVS 304 Instruction code JNC EXIT Example 01010000 70 Byte 1 Before execution After execution : Program counter 15 8 0000100000110101 70 Program counter 15 8 0000100001011001 .
DESCRIPTION OF INSTRUCTIONS 305 48. JNZ code address (Jump if accumulator is not 0) 01110000 70 Instruction code Relative offset Operations Number of bytes Number of cycles Flags (PSW) Description : B.
MSM80C154S/83C154S/85C154HVS 306 Instruction code JNZ TEST Example 01110000 70 Byte 1 Before execution After execution : Program counter 15 8 0000000011111100 70 Program counter 15 8 0000000100101110 .
DESCRIPTION OF INSTRUCTIONS 307 49. JZ code address (Jump if accumulator is not 0) 01100000 70 Instruction code Relative offset Operations Number of bytes Number of cycles Flags (PSW) Description : By.
MSM80C154S/83C154S/85C154HVS 308 Instruction code JZ EMPTY Example 01100000 70 Byte 1 Before execution After execution : Program counter 15 8 0000000011001010 70 Program counter 15 8 0000000010011001 .
DESCRIPTION OF INSTRUCTIONS 309 50. LCALL code address (Long call) 00010010 70 Instruction code Call address Call address Operations Number of bytes Number of cycles Flags (PSW) Description : Byte 1 A.
MSM80C154S/83C154S/85C154HVS 310 51. LJMP code address (Long jump) 00000010 70 Instruction code Jump address Jump address Operation Number of bytes Number of cycles Flags (PSW) Description : Byte 1 A .
DESCRIPTION OF INSTRUCTIONS 311 52. MOV @Rr, #data (Move immediate data to indirect address) 0111011 r 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Descripti.
MSM80C154S/83C154S/85C154HVS 312 53. MOV @Rr, A (Move accumulator to indirect address) 1111011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example MOV @R0,.
DESCRIPTION OF INSTRUCTIONS 313 54. MOV @Rr, data address (Move memory to indirect address) 1010011 r 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Descriptio.
MSM80C154S/83C154S/85C154HVS 314 55. MOV A, #data (Move immediate data to accumulator) 01110100 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Description Example MOV.
DESCRIPTION OF INSTRUCTIONS 315 56. MOV A, @Rr (Move indirect address to accumulator) 1110011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example MOV A, @R.
MSM80C154S/83C154S/85C154HVS 316 57. MOV A, Rr (Move register to accumulator) 11101 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example MOV A, R6.
DESCRIPTION OF INSTRUCTIONS 317 58. MOV A, data address (Move memory to accumulator) 11100101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description Exampl.
MSM80C154S/83C154S/85C154HVS 318 59. MOV C, bit address (Move bit to carry flag) 10100010 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example MOV C, P3.
DESCRIPTION OF INSTRUCTIONS 319 60. MOV DPTR, #data (Move immediate data to data pointer) 10010000 70 Instruction code #data #data Operation Number of bytes Number of cycles Flags (PSW) Description Ex.
MSM80C154S/83C154S/85C154HVS 320 61. MOV Rr, #data (Move immediate data to register) 01111 r 2 r 1 r 0 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Description Exam.
DESCRIPTION OF INSTRUCTIONS 321 62. MOV Rr, A (Move accumulator to register) 11111 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example MOV R1, A Instruction code : Byte 1 (Rr) ← (A) r=0 thru 7 : C AC F0 RS1 RS0 OV F1 P : : : The accumulator contents are copied to the register r.
MSM80C154S/83C154S/85C154HVS 322 63. MOV Rr, data address (Move memory to register) 10101 r 2 r 1 r 0 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Descriptio.
DESCRIPTION OF INSTRUCTIONS 323 64. MOV bit address, C (Move carry flag to bit) 10010010 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example MOV P1.
MSM80C154S/83C154S/85C154HVS 324 65. MOV data address, #data (Move immediate data to memory) 01110101 70 Instruction code Data address #data Operation Number of bytes Number of cycles Flags (PSW) Desc.
DESCRIPTION OF INSTRUCTIONS 325 66. MOV data address, @Rr (Move indirect address to memory) 1000011 r 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Descriptio.
MSM80C154S/83C154S/85C154HVS 326 67. MOV data address, A (Move accumulator to memory) 11110101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description Examp.
DESCRIPTION OF INSTRUCTIONS 327 68. MOV data address, Rr (Move register to memory) 10001 r 2 r 1 r 0 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description.
MSM80C154S/83C154S/85C154HVS 328 69. MOV data address 1, data address 2 (Move memory to memory) 10000101 70 Instruction code Data address 2 Data address 1 Operation Number of bytes Number of cycles Fl.
DESCRIPTION OF INSTRUCTIONS 329 70. MOVC A, @A + DPTR (Move code memory offset from data pointer to accumulator) 10010011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Des.
MSM80C154S/83C154S/85C154HVS 330 71. MOVC A, @A + PC (Move code memory offset from program counter to accumulator) 10000011 70 Instruction code Operations Number of bytes Number of cycles Flags (PSW) .
DESCRIPTION OF INSTRUCTIONS 331 72. MOVX @DPTR, A (Move accumulator to external memory addressed by data pointer) 11110000 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) De.
MSM80C154S/83C154S/85C154HVS 332 73. MOVX @Rr, A (Move accumulator to external memory addressed by register) 1111001 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Descri.
DESCRIPTION OF INSTRUCTIONS 333 74. MOVX A, @DPTR (Move external memory addressed by data pointer to accumulator) 11100000 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) De.
MSM80C154S/83C154S/85C154HVS 334 75. MOVX A, @Rr (Move external memory addressed by register to accumulator) 1110001 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Descri.
DESCRIPTION OF INSTRUCTIONS 335 76. MUL AB (Multiply accumulator by B) 10100100 70 Instruction code Operations Number of bytes Number of cycles Flags (PSW) Description Example MUL AB(6AH × 15H=8B2H) .
MSM80C154S/83C154S/85C154HVS 336 77. NOP (No operation) 00000000 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description : Byte 1 (PC) ← (PC)+1 : C AC F0 RS1 RS0 OV F1 P : : : The program counter is incremented by 1 without any other change in the CPU.
DESCRIPTION OF INSTRUCTIONS 337 78. ORL A, #data (Logical OR immediate data to accumulator) 01000100 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Description Exampl.
MSM80C154S/83C154S/85C154HVS 338 79. ORL A, @Rr (Logical OR indirect address to accumulator) 0100011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example OR.
DESCRIPTION OF INSTRUCTIONS 339 80. ORL A, Rr (Logical OR register to accumulator) 01001 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example ORL .
MSM80C154S/83C154S/85C154HVS 340 81. ORL A, data address (Logical OR memory to accumulator) 01000101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description.
DESCRIPTION OF INSTRUCTIONS 341 82. ORL C, bit address (Logical OR bit to carry flag) 01110010 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example ORL C, ACC.
MSM80C154S/83C154S/85C154HVS 342 83. ORL C,/bit address (Logical OR complement of bit to carry flag) 10100000 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example ORL C,/25H.
DESCRIPTION OF INSTRUCTIONS 343 84. ORL data address, #data (Logical OR immediate data to memory) 01000011 70 Instruction code Data address #data Operation Number of bytes Number of cycles Flags (PSW).
MSM80C154S/83C154S/85C154HVS 344 85. ORL data address, A (Logical OR accumulator to memory) 01000010 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Description.
DESCRIPTION OF INSTRUCTIONS 345 86. POP data address (Pop stack to memory) 11010000 70 Instruction code Data address Operations Number of bytes Number of cycles Flags (PSW) Description Example POP PSW:No change to parity bit.
MSM80C154S/83C154S/85C154HVS 346 87. PUSH data address (Push memory onto stack) 11000000 70 Instruction code Data address Operations Number of bytes Number of cycles Flags (PSW) Description Example PU.
DESCRIPTION OF INSTRUCTIONS 347 88. RET (Return from subroutine, non interrupt) 00100010 70 Instruction code Operations Number of bytes Number of cycles Flags (PSW) Description : Byte 1 (PC 8~15 ) ←.
MSM80C154S/83C154S/85C154HVS 348 89. RETI (Return from interrupt routine) 00110010 70 Instruction code Operations Number of bytes Number of cycles Flags (PSW) Description : Byte 1 (PC 8~15 ) ← ((SP).
DESCRIPTION OF INSTRUCTIONS 349 90. RL A (Rotate accumulator left) 00100011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example RL A Instruction code : Byte 1 : C AC F0 RS1 RS0 OV F1 P : : : All accumulator bits are shifted by one bit to the left.
MSM80C154S/83C154S/85C154HVS 350 91. RLC A (Rotate accumulator and carry flag left) 00110011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example RLC A Instru.
DESCRIPTION OF INSTRUCTIONS 351 92. RR A (Rotate accumulator right) 00000011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example RR A Instruction code : Byte 1 : C AC F0 RS1 RS0 OV F1 P : : : All accumulator bits are shifted by one bit to the right.
MSM80C154S/83C154S/85C154HVS 352 93. RRC A (Rotate accumulator and carry flag right) 00010011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example RRC A Instr.
DESCRIPTION OF INSTRUCTIONS 353 94. SETB C (Set carry flag) 11010011 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example SETB C Instruction code : Byte 1 (C) ← 1 : C AC F0 RS1 RS0 OV F1 P • : : : The carry flag is cleared to 1.
MSM80C154S/83C154S/85C154HVS 354 95. SETB bit address (Set bit) 11010010 70 Instruction code Bit address Operation Number of bytes Number of cycles Flags (PSW) Description Example SETB IE.
DESCRIPTION OF INSTRUCTIONS 355 96. SJMP code address (Short jump) 10000000 70 Instruction code Relative offset Operations Number of bytes Number of cycles Flags (PSW) Description : Byte 1 (PC) ← (P.
MSM80C154S/83C154S/85C154HVS 356 Instruction code SJMP CHECK Example 10000000 70 Byte 1 Before execution After execution : Program counter 15 8 0000000100010001 70 Program counter 15 8 000000010010001.
DESCRIPTION OF INSTRUCTIONS 357 97. SUBB A, #data (Substract immediate data from accumulator with borrow) 10010100 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Desc.
MSM80C154S/83C154S/85C154HVS 358 98. SUBB A, @Rr (Substract indirect address from accumulator with borrow) 1001011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Descript.
DESCRIPTION OF INSTRUCTIONS 359 99. SUBB A, Rr (Substract register from accumulator with borrow) 10011 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Descriptio.
MSM80C154S/83C154S/85C154HVS 360 100. SUBB A, data address (Substract memory from accumulator with borrow) 10010100 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (P.
DESCRIPTION OF INSTRUCTIONS 361 101. SWAP A (Exchange nibble in accumulator) 11000100 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example SWAP A Instruction .
MSM80C154S/83C154S/85C154HVS 362 102. XCH A, @Rr (Exchange indirect address with accumulator) 1100011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example X.
DESCRIPTION OF INSTRUCTIONS 363 103. XCH A, Rr (Exchange register with accumulator) 11001 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description Example XCH.
MSM80C154S/83C154S/85C154HVS 364 104. XCH A, data address (Exchange memory with accumulator) 11000101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) Descriptio.
DESCRIPTION OF INSTRUCTIONS 365 105. XCHD A, @Rr (Exchange low nibbles of indirect address with accumulator) 1101011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Descri.
MSM80C154S/83C154S/85C154HVS 366 106. XRL A, #data (Logical exclusive OR immediate data to accumulator) 01100100 70 Instruction code #data Operation Number of bytes Number of cycles Flags (PSW) Descri.
DESCRIPTION OF INSTRUCTIONS 367 107. XRL A, @Rr (Logical exclusive OR indirect address to accumulator) 0110011 r 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description .
MSM80C154S/83C154S/85C154HVS 368 108. XRL A, Rr (Logical exclusive OR register to accumulator) 01101 r 2 r 1 r 0 70 Instruction code Operation Number of bytes Number of cycles Flags (PSW) Description .
DESCRIPTION OF INSTRUCTIONS 369 109. XRL A, data address (Logical exclusive OR memory to accumulator) 01100101 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) D.
MSM80C154S/83C154S/85C154HVS 370 110. XRL data address, #data (Logical exclusive OR immediate data to memory) 01100011 70 Instruction code Data address #data Operation Number of bytes Number of cycles.
DESCRIPTION OF INSTRUCTIONS 371 111. XRL data address, A (Logical exclusive OR accumulator to memory) 01100010 70 Instruction code Data address Operation Number of bytes Number of cycles Flags (PSW) D.
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