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Intel ® Pentium ® D Processor 800 Δ Sequence Datasheet – On 90 nm Process in the 775- land LGA Package and supporting Intel ® Extended Memory 64 T echnology Φ February 2006 Document Number: 307.
2 Datasheet Contents INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WI TH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMP LIED, BY ESTOPPEL OR OT HERWISE, TO ANY INTELL ECTUAL PROPERTY RIGH TS IS GRANTED BY THIS DOCUMENT .
Datasheet 3 Contents Contents 1 Introduction ................ ................ ............. ................ ................ ................ ............. ........ .................. 11 1.1 Terminology .............. ............. ................ .
4 Datasheet Contents 5.2 Processor Thermal Features .... ................ ................ ................ ................ ................ .......... 79 5.2.1 Thermal Monitor.... ................ ................ ................. ................ .
Datasheet 5 Contents Figures 2-1 VCC Static and Transient Tolerance for 775 _VR_CONFIG_05A Pentium D Process or ............ 22 2-2 VCC Static and Transient Tolerance for 775 _VR_CONFIG_05B Pentium D Process or ............ 24 2-3 VCC Overshoot Example Waveform .
6 Datasheet Contents Tables 1-1 References ......... ................. ................ ............. ................ ................ ............. .............. ........ ....... 13 2-1 Voltage Identification Definit ion .............. ............
Datasheet 7 Contents Revision History § Revision Number Description Date -001 • Initial release May 2005 -002 • Added Balanced T echnology Extended (BTX) T ype I Boxed Processor S pecifications chapter . October 2005 -003 • Added Intel ® Pentium ® D processor 805 specifications.
8 Datasheet Contents.
Datasheet 9 Contents Intel ® Pentium ® D Processor 800 Sequence Features The Intel ® Pentium ® D processor delivers Intel's adv anced, powerful processors for desktop PCs that are based on the Intel NetBurst ® microarchitecture.
10 Datasheet Contents.
Datasheet 11 Introduction 1 Introduction The Intel ® Pentium ® D processor extends Intel's Desktop dual-core pro duct line. The Pentium D processor uses Flip-Chip Land Gri d Array (FC- LGA4) package technology , and plugs into a 775- land LGA socket, referred to as the LGA775 socket.
12 Datasheet Introduction 1.1 T erminology A ‘#’ symbol after a signal name ref ers to an ac tive low signal, indicating a signal is in th e active state when driven to a low level. For example, when RESET# is low , a reset has been requested. Conversely , when NMI is high, a nonmaskable inte rrupt has occurred.
Datasheet 13 Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: § T able 1- 1. References Document Document Locatio n Intel ® Pentium ® D Processor and Intel ® Pentium ® Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines http://developer .
14 Datasheet Introduction.
Datasheet 15 Electrical Specifications 2 Electrical Specifications This chapter describes the elect rical characteristics of the pro cessor interfaces and signals.
16 Datasheet Electrical Specifications 2.2.3 FSB Decoupling The Pentium D processor package in tegrates signal termination on the die as well as incorporates high frequency decoupling capacitan ce on the processor package. Decoupling must also be provided by the system baseboard for proper G TL+ bus operation.
Datasheet 17 Electrical Specifications T able 2-1. V oltage Identific ation Definition VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VI D4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.
18 Datasheet Electrical Specifications 2.4 Reserved, Unused, FC and TESTHI Signals All RESER VED lands m ust remain unconnected. Connection of these lands to V CC , V SS , V TT , or to any other signal (including each other) can re sult in component malfunction or incomp atibility with future processors.
Datasheet 19 Electrical Specifications 2.5 V olt age and Current S pecifications 2.5.1 Absolute Maximum and Minimum Ratings Ta b l e 2 - 2 specifies absol ute maximum and minimu m ratings. W ithin function al operation limits, functionality and long-t erm reliability can be expected.
20 Datasheet Electrical Specifications T able 2-3. V o lt age and Current Specifications Symbol Parameter Min T yp Max Unit Notes VID range VID 1.200 — 1.400 V 1 NOTES: 1. Individual processor VID va lues may be calibrated during manufactu ring such that two devices at the sa me speed may have diffe rent VID setting s.
Datasheet 21 Electrical Specifications 5. 775_VR_CONFIG_0 5A and 775_VR_CONFIG_05B refer to voltage regulato r configurations that are defined in the Voltage Regulat or Down (VRD) 10.1 Design Guide For Desktop LGA775 Socke t . 6. Refer to Table 2-4 and Figure 2-1 for the minimum, t ypical, and maximum V CC allowed for a given curren t.
22 Datasheet Electrical Specifications NOTES: 1. T he loadline specification includes bot h static and transi ent limits except for overshoot allowed as shown in Section 2.5.3 . 2. T his loadline specific ation shows the deviation from the VID set point.
Datasheet 23 Electrical Specifications T able 2-5. V CC St atic and T ransien t T olerance fo r 775_VR_CONFIG_05B Pentium D Processor Icc (A) V olt age De viation from VI D Setting (V) 1, 2, 3 NOTES: 1. The loadline specificat ion includes both static and transient limits exce pt for overshoot allowed as shown in Section 2.
24 Datasheet Electrical Specifications Figure 2-2. V CC St atic and T ra nsient T ole rance for 775_VR_CONFIG_05B Pentium D Processor VID - 0.000 VID - 0.
Datasheet 25 Electrical Specifications 2.5.3 V CC Overshoot S pecification The Pentium D processo r can tolerate s hort transient overs hoot events where V CC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + V OS_MAX (V OS_MAX is the maximum allowable overshoot voltag e).
26 Datasheet Electrical Specifications 2.5.4 Die V o lt age V a lidation Overshoot events on the processor must meet the specifications in Ta b l e 2 - 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events th at are < 10 ns in durat ion may be ignored.
Datasheet 27 Electrical Specifications Ta b l e 2 - 8 outlines the signals which in clude on-die termination (R TT ). Open drain signals are also included. Ta b l e 2 - 9 provides signal reference voltages. T able 2-7. FSB Signal Group s Signal Group T ype Signals 1 NOTES: 1.
28 Datasheet Electrical Specifications 2.6.2 G TL+ Asynchronous Signals The signals A20M#, IGNNE#, INIT#, SMI#, a nd STPCLK# utilize CMOS input buffers. G TL+ asynchronous si gnals follow t he same DC requirem ents as G TL+ signals; however , the outputs are not actively driven high (duri ng a logical 0 to 1 transition) by the processor .
Datasheet 29 Electrical Specifications 2.6.3 FSB DC Specifications The processor front side bus DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated .
30 Datasheet Electrical Specifications T able 2-12. PWRGOOD Input and T A P Signal Group DC Specif ications Symbol Parameter Min Max Unit Notes 1, 2 NOTES: 1. Unless otherwise noted, all specifi cations in this table apply to all processor frequencies.
Datasheet 31 Electrical Specifications 2.6.3.1 G TL+ Front Si de Bus Specifications In most cases, termination resist ors are not requ ired as these are integr ated into the processor silicon. See Ta b l e 2 - 8 for deta ils on which G TL+ signals do not include on-di e termination.
32 Datasheet Electrical Specifications 2.7 Clock Specifications 2.7.1 FSB Clock (BCLK[1:0 ]) and Processor Clocking BCLK[1:0] directly controls the FS B interface speed as well as the core frequency of the processor . As in previous generation processors, the Pentium D processor core frequency is a multiple of the BCLK[1:0] frequency .
Datasheet 33 Electrical Specifications 2.7.3 Phase Lock Loop (PLL) and Filter V CCA and V CCIOPLL are power sources required by the PL L clock generators for the Pentium D processor. Since these PL Ls are analog in nature, they require quiet power suppl ies for minimum jitter .
34 Datasheet Electrical Specifications NOTES: 1. Diagr am not to scale. 2. No specifications for frequenc ies beyond fcore (core fre quency). 3. fpeak, if existent, should be less than 0.05 MHz. 4. fcore r epresents the maximum core frequency supported by the platform.
Datasheet 35 Package Mechanical Specifications 3 Package Mechanical Specifications The Intel ® Pentium ® D processor is packaged in a Flip-C hip Land Grid Array (FC-LGA4) package that interfaces with the moth erboard via an LGA 775 socket. The package consists of a processor core mounted on a substrate land-carrier .
36 Datasheet Package Mechanic al Specifications Figure 3-2. Processor Package Drawing 1.
Datasheet 37 Package Mechanical Specifications Figure 3-3. Processor Package Drawing 2.
38 Datasheet Package Mechanic al Specifications Figure 3-4. Processor Package Drawing 3.
Datasheet 39 Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contai n components on the substrate that define component keep-out zone requirements. A therm al and mechanical solution design must not intrude i nto the required keep - out zones.
40 Datasheet Package Mechanic al Specifications 3.5 Package Insertion S pecifications The Pentium D processor can be inserted int o and removed from a LGA775 socket 15 times. The socket should m eet the LGA775 req uirements detailed in the LGA775 So cket Mechanical D esign Guide .
Datasheet 41 Package Mechanical Specifications Figure 3-6. Proces sor T op-Side Marking Example (Intel ® Pentium ® D Processor 805) ATPO S/N Processor Num ber/ S-Spec/ Country of Assy INTEL XXXXXXXX 2.
42 Datasheet Package Mechanic al Specifications 3.9 Processor Land Coordinates Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to throughout the docum ent to identify processor lands.
43 Datasheet Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the p rocessor land assignment and si gnal descriptions. 4.1 Processor Land Assignment s This section contains the land listings for the Intel ® Pentium ® D processor.
44 Datasheet Land Listing and Signal Descriptions Figure 4-1. Landout Diagram (T op View – Lef t Side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VS S.
Datasheet 45 Land Listing and Signal Descriptions Figure 4-2. Landou t Diagram (T op View – Right Side) 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 VCC VS S VCC VCC VSS VCC VCC FC16 VSS_MB_ REGULA TION VCC_MB.
Land Listing and Signal Descriptions 46 Datasheet T able 4-1. Alphabetical Land Assignment s Land Name Land # Signal Buffer Ty p e Direction A3# L5 Source Synch Input/Output A4# P6 Source Synch Input/.
Land Listing and Signal Descr iptions Datasheet 47 D21# E10 Source Syn ch Input/Output D22# D10 Source Syn ch Input/Output D23# F1 1 Source Synch Input/Output D24# F12 Source Synch Input/Outp ut D25# .
Land Listing and Signal Descriptions 48 Datasheet G TLREF1 H2 Power/Other Input HIT# D4 Common Clo ck Input/Output HITM# E 4 Common Clock Input/Output IERR# AB2 Asynch G TL+ Output IGNNE# N2 Asynch G .
Land Listing and Signal Descr iptions Datasheet 49 VCC A C27 Power /Othe r VCC A C28 Power /Othe r VCC A C29 Power /Othe r VCC A C30 Power /Othe r VCC AC8 Power/Other VCC A D23 Power /Othe r VCC A D24.
Land Listing and Signal Descriptions 50 Datasheet VCC AK14 Power /Other VCC AK15 Power /Other VCC AK18 Power /Other VCC AK19 Power /Other VCC AK21 Power /Other VCC AK22 Power /Other VCC AK25 Power /Ot.
Land Listing and Signal Descr iptions Datasheet 51 VCC K30 Power/Oth er VCC K8 P ower/ Other VCC L8 Power/ Other VCC M23 Power/Other VCC M24 Power/Other VCC M25 Power/Other VCC M26 Power/Other VCC M27.
Land Listing and Signal Descriptions 52 Datasheet VSS AA24 Power/Oth er VSS AA25 Power/Oth er VSS AA26 Power/Oth er VSS AA27 Power/Oth er VSS AA28 Power/Oth er VSS AA29 Power/Oth er VSS AA3 Power/Othe.
Land Listing and Signal Descr iptions Datasheet 53 VSS AJ23 Power/Other VSS AJ24 Power/Other VSS AJ27 Power/Other VSS AJ28 Power/Other VSS AJ29 Power/Other VSS AJ30 Power/Other VSS AJ4 Power/Other VSS.
Land Listing and Signal Descriptions 54 Datasheet VSS E1 1 Power/Other VSS E14 Power/Other VSS E17 Power/Other VSS E2 Power/Other VSS E20 Power/Other VSS E25 Power/Other VSS E26 Power/Other VSS E27 Po.
Land Listing and Signal Descr iptions Datasheet 55 VSS R30 Power/Othe r VSS R5 Power/Other VSS R7 Power/Other VSS T3 Power/Other VSS T6 Power/Other VSS T7 Power/Other VSS U1 Power/Other VSS U7 Power/O.
Land Listing and Signal Descriptions 56 Datasheet T able 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Ty p e Direction A2 VSS Power/Other A3 RS2# Common Clock Input A4 D2# Source Sync.
Land Listing and Signal Descr iptions Datasheet 57 C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Other C29 VTT Power/Other C30 VTT Power/Other D1 RESER .
Land Listing and Signal Descriptions 58 Datasheet F19 VSS Power/Other F20 D41# Source Synch Input/Output F21 D43# Source Synch Input/Output F22 VSS Power/Other F23 RESERVED F24 TESTHI7 Power/Other Inp.
Land Listing and Signal Descr iptions Datasheet 59 J12 VCC Power/Other J13 VCC Power/Other J14 VCC Power/Other J15 VCC Power/Other J16 DP0# Common Clock Input/Output J17 DP3# Common Clock Input/Output.
Land Listing and Signal Descriptions 60 Datasheet N30 VCC Power/Other P1 TESTHI1 1 Power/Other Input P2 SMI# Asynch G TL+ Input P3 INIT# Asynch G TL+ Input P4 VSS Power/Other P5 RESERVED P6 A4# Source.
Land Listing and Signal Descr iptions Datasheet 61 W2 TESTHI12 Power/Other Input W3 TESTHI1 Power/Oth er Input W4 VSS Power/ Other W5 A16# Source Synch Input/Output W6 A18# Source Synch Input/Output W.
Land Listing and Signal Descriptions 62 Datasheet AD4 VSS Power/Other AD5 ADSTB1# Source Synch Input/Output AD6 A22# Source S ynch Input/Output AD7 VSS Power/Other AD8 VCC Power/Other AD23 VCC P ower/.
Land Listing and Signal Descr iptions Datasheet 63 AG10 VSS Power/ Other AG1 1 VCC Pow er/Ot her AG12 VCC P ower/O ther AG13 VSS Power/ Other AG14 VCC P ower/O ther AG15 VCC P ower/O ther AG16 VSS Pow.
Land Listing and Signal Descriptions 64 Datasheet AK2 VS S Power/Other AK3 ITP_CLK0 T AP Input AK4 VID4 Power/Other Output AK5 VS S Power/Other AK6 FORCEPR# Asynch G TL+ Input AK7 VS S Power/Other AK8.
Land Listing and Signal Descr iptions Datasheet 65 AM24 VSS Power/Other AM25 VCC P ower/Ot her AM26 VCC P ower/Ot her AM27 VSS Power/Other AM28 VSS Power/Other AM29 VCC P ower/Ot her AM30 VCC P ower/O.
66 Datasheet Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference T able 4-3. Signal Description (Sheet 1 of 8) Name T ype Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory a ddress space. In sub- phase 1 of the address phase, these signals transmit the a ddress of a transaction.
Datasheet 67 Land Listing and Signal Descriptions BINIT# Input/ Output BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropr iate pins/lands of all such agents.
68 Datasheet Land Listing and Signal Descriptions D[63:0]# Input/ Output D[63:0]# (Data) are the data signals. Th ese signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents.
Datasheet 69 Land Listing and Signal Descriptions DRDY# Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer , DRDY# may be de-asserted to insert idle clocks.
70 Datasheet Land Listing and Signal Descriptions IERR# Output IERR# (Internal Error) is asserted by a pr ocessor as the result of an internal error . Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transacti on may optionally be converted to an external error signal (e.
Datasheet 71 Land Listing and Signal Descriptions MCERR# Input/ Output MCERR# (Machine Check Error) is asserted to indicate a n unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are config urable at a system level.
72 Datasheet Land Listing and Signal Descriptions RSP# Input RSP# (Response Parity) is driven by t he response agent (the agent responsible for completion of the current transaction) during a ssertion of RS[2:0]#, the signals for which RSP# provides parity protection.
Datasheet 73 Land Listing and Signal Descriptions § TMS Input TMS (T est Mode Select) is a JT AG spec ification support signal used by debug tools. TRDY# Input TRDY# (T arget Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer .
74 Datasheet Land Listing and Signal Descriptions.
Datasheet 75 Thermal Specifications a nd Design Considerat ions 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal S pecifications The Intel ® Pentium ® D processor requires a thermal solutio n to maintain temperatures within operatin g limits as set for th in Section 5.
76 Datasheet Thermal Specificat ions and Design Considerations Refer to the Intel ® Pentium ® D Pr ocessor and Intel ® Pentium ® Pr ocessor Extr eme Edition 840 Thermal and Mechanical Design Guidelines and the Pr ocessor Power Characterization Methodology for the detai ls of this methodology .
Datasheet 77 Thermal Specifications a nd Design Considerat ions T able 5-2. Thermal Profile for the Pentium D Processor with PRB=1 Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) 0 43.8 34 50.
78 Datasheet Thermal Specificat ions and Design Considerations T able 5-3. Thermal Profile for the Pentium D Processor with PRB=0 Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) Power (W) Maximum T C (°C) 0 43.2 26 48.
Datasheet 79 Thermal Specifications a nd Design Considerat ions 5.1.2 Thermal Metrology The maximum and minimum case temperatures (T C ) are specified in Ta b l e 5 - 1 . These temperature specifications are meant to help ensure proper operation of the processor .
80 Datasheet Thermal Specificat ions and Design Considerations W ith a properly designed and char acterized thermal solu tion, it is anticipated that the TCC would only be activated for very short perio ds of time when running the most pow er intensive applications.
Datasheet 81 Thermal Specifications a nd Design Considerat ions As a bi-directional signal, PROCHOT# allows for some protection of various com ponents from over-temperature situations.
82 Datasheet Thermal Specificat ions and Design Considerations 5.2.5 THERMTRIP# Signal Regardless of whether or not t he Thermal Monitor f eature is enabled, in th e event of a catastrophic cooling fa.
Datasheet 83 Thermal Specifications a nd Design Considerat ions § T able 5-5. Thermal Diode Interface Signal Name Land Numb er Signal Description THERMDA AL1 diode anode THERMDC AK1 diode cathode.
84 Datasheet Thermal Specificat ions and Design Considerations.
Datasheet 85 Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardw are. The Intel ® Pentium ® D processor samples the hardware configuration at reset, on the active-to-in active transition of RESET#.
86 Datasheet Features 6.2.1 Normal St ate This is the normal operatin g state for the processor . 6.2.2 HAL T and Enhanced HAL T Powerdown St ates The Pentium D processor supports the HAL T or En hanced HAL T powerdown stat e. The Enhanced HAL T Powerdown state is config ured and enabled via the BIOS.
Datasheet 87 Features The system can generate a STPCLK# while the processor is in the HAL T Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HAL T state. While in HAL T Power Down state, the processor wil l process bus snoops.
88 Datasheet Features 6.2.4 Enhanced HAL T Snoop or HA L T Snoop St ate, Grant Sno op State The Enhanced HAL T Snoop State is used in conj unction with the ne w En hanced HAL T state. If Enhanced HAL T state is not enabled in the BIOS , the default Snoop State entered will be the HAL T Snoop State.
Datasheet 89 Boxed Processor Specifications 7 Boxed Processor Specifications The Intel ® Pentium ® D processor will also be offered as an Intel boxed processor . Intel boxed processors are intended for system integrators who buil d systems from baseboard s and standard components.
90 Datasheet Boxed Processor Specificat ions 7.1 Mechanical S pecifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mech anical specifications of the box ed Pentium D proc essor. The boxed processor will be shipped with an unattached fan heatsink.
Datasheet 91 Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heat sink Weight The boxed processor fan heatsink will no t weigh more than 550 grams.
92 Datasheet Boxed Processor Specificat ions The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connecto r labeled as CONTROL. The boxed processor's fan heatsi nk requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM cont rol.
Datasheet 93 Boxed Processor Specifications 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor . 7.3.1 Boxed Processor Cooling Requirement s The boxed processor may be direct ly cooled with a fan heatsink.
94 Datasheet Boxed Processor Specificat ions Figure 7-7. Boxed Processor Fan He atsink Airs pace Keepout Re quirements (side 1 view) Figure 7-8. Boxed Processor Fan He atsink Airs pace Keepout Re quir.
Datasheet 95 Boxed Processor Specifications 7.3.2 V ariable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin m otherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures.
96 Datasheet Boxed Processor Specificat ions If the boxed processor fan heatsink 4-pin con nector is connected to a 4-pin motherboard header and the motherboard is desi gned with a fan speed controlle.
Datasheet 97 Balanced T echnology Ext ended (BTX) T ype I Boxed Processor Specifications 8 Balanced T echnology Extended (BTX) T ype I Boxed Processor Specifications The Intel ® Pentium ® D processor will also be offered as an boxed Intel processor .
98 Datasheet Balanced T echnology Extended ( BTX) Ty pe I Boxed Processor Specifications 8.1 Mechanical S pecifications 8.1.1 Cooling Solution Dimensions This section documents the mech anical specifications of the box ed Pentium D processor TMA. The boxed processor will be shi pped with an unattached TMA.
Datasheet 99 Balanced T echnology Ext ended (BTX) T ype I Boxed Processor Specifications 8.1.3 Boxed Processor Support and Retention Module (SRM) The boxed processor TMA requires a SRM assembly to attach directly to th e chassis base pan and to secure the processor and TMA in the mainboa rd socket.
100 Datasheet Balanced T echnology Extended ( BTX) Ty pe I Boxed Processor Specifications The fan heatsink receives a PWM s igna l from the motherb oard from the 4 th pin of the connector labeled as CONTROL.
Datasheet 101 Balanced T echnology Ext ended (BTX) T ype I Boxed Processor Specifications 8.3 Thermal Specifications This section describes the cooling requirements o f the fan heatsink solution used by the boxed processor . 8.3.1 Boxed Processor Cooling Requirement s The boxed processor may be direct ly cooled with a fan heatsink.
102 Datasheet Balanced T echnology Extended ( BTX) Ty pe I Boxed Processor Specifications 8.3.2 V ariable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherbo.
Datasheet 103 Balanced T echnology Ext ended (BTX) T ype I Boxed Processor Specifications If the boxed processor TMA 4-pin connector is co nnected to a 4-pin moth erboard header and the motherboard is.
104 Datasheet Balanced T echnology Extended ( BTX) Ty pe I Boxed Processor Specifications.
Datasheet 10 5 Debug Tools Specificat ions 9 Debug T ools Specifications Refer to the eXtended Debug Port: Deb ug Port Design Guide for UP and DP Platforms and the ITP700 Debug Port Design Gu ide for information reg arding debug tools specification s.
106 Datasheet Debug T ools Specifications.
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